Displaying 20 results from an estimated 300 matches similar to: "confint function in MASS package for logistic regression analysis"
2007 Oct 11
1
constraining correlations
Hello,
I've searched for an answer to no avail. I am wondering if anyone
knows how to constrain certain correlations to be equal. I have family
data with 2 twins per family plus up to 2 siblings. I would like to
somehow constrain all the sibling correlations (twin-sib and sib-sib)
to be the same while allowing the twin-twin correlation to be
different. Here is some simulated code:
2013 Sep 12
1
[LLVMdev] bug in X86 disasm code?
hi,
i found this code in X86DisassemblerDecoder.h
#define EA_BASES_32BIT \
ENTRY(EAX) \
ENTRY(ECX) \
ENTRY(EDX) \
ENTRY(EBX) \
ENTRY(sib) \
ENTRY(EBP) \
ENTRY(ESI) \
ENTRY(EDI) \
ENTRY(R8D) \
ENTRY(R9D) \
ENTRY(R10D) \
ENTRY(R11D) \
2006 May 30
1
sib TDT transmission/disequilibrium test
Does anyone know if the sib TDT has been implemented in R
1. Spielman, R.S., and Ewens, W.J. (1998) A sibship test for linkage in the
presence of association: the sib transmission/disequilibrium test. Am J Hum
Genet 62, 450-458
--
Farrel Buchinsky, MD
Pediatric Otolaryngologist
Allegheny General Hospital
Pittsburgh, PA
2009 May 05
2
[LLVMdev] [PATH] Fixes for the amd64 JIT code
Hi Zoltan,
The part that determines whether SIB byte is needed caused a lot of
regressions last night (see Geryon-X86-64 etc.). I've reverted it for
now. Please take a look.
Thanks,
Evan
On May 4, 2009, at 3:49 PM, Evan Cheng wrote:
> Committed as revision 70929. Thanks.
>
> Evan
>
> On May 3, 2009, at 8:29 PM, vargaz wrote:
>
>>
>> Hi,
>>
>>
2009 May 05
1
[LLVMdev] [PATH] Fixes for the amd64 JIT code
Hi,
It looks like the problem was with the RIP relative addressing. The
original patch mistakenly
removed the || DispForReloc part because I tough that the RIP relative
addressing was done
by the SIB encodings, but it is actually done by the shorter ones.
The attached patch seems to work for me on linux and when simulating darwin
by forcing some variables in X86TargetMachine.cpp to their darwin
2009 May 05
0
[LLVMdev] [PATH] Fixes for the amd64 JIT code
Hi,
I can't reproduce these failures on my linux machine. The test machine
seems to be
running darwin. I suspect that the problem might be with RIP relative
addressing, or with
the encoding of R12/R13, but the code seems to handle the latter, since it
checks for
ESP/EBP which is the same as R12/R13.
Zoltan
On Tue, May 5, 2009 at 8:18 PM, Evan Cheng <evan.cheng at
2009 May 04
3
[LLVMdev] [PATH] Fixes for the amd64 JIT code
Hi,
If this looks ok, could somebody check it in ?
thanks
Zoltan
Evan Cheng-2 wrote:
>
> Looks good. Thanks.
>
> Evan
>
> On May 1, 2009, at 8:40 AM, Zoltan Varga wrote:
>
>> Hi,
>>
>> The attached patch contains the following changes:
>>
>> * X86InstrInfo.cpp: Synchronize a few places with the code
2016 Nov 23
4
RFC: code size reduction in X86 by replacing EVEX with VEX encoding
Hi All.
This is an RFC for a proposed target specific X86 optimization for reducing code size in the encoding of AVX-512 instructions when possible.
When the AVX512F instruction set was introduced in X86 it included additional 32 registers of 512bit size each ZMM0 - ZMM31, as well as additional 16 XMM registers XMM16-XMM31 and 16 YMM registers YMM16-YMM31.
In order to encode the new registers of
2008 May 06
4
categorical data analysis
hie all
i am trying to carry out a categorical data analysis but my problem is that when in i use the chi squared test some of my expected values are less than 5. is there a test that can handle this situation. the data is not a 2*2 table. its more from the social sciences where you have from strongly agree to strongly disagree. i know i can collapse vthe tables but there is a loss of
2009 May 01
2
[LLVMdev] [PATH] Fixes for the amd64 JIT code
Hi,
The attached patch contains the following changes:
* X86InstrInfo.cpp: Synchronize a few places with the code in
X86CodeEmitter.cpp
* X86CodeEmitter.cpp: Avoid the longer SIB encoding on amd64 if it is not
neeed.
Zoltan
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2008 Jan 10
2
Switch from courier to dovecot
I have an courier IMAP server running. To get sib dirs working I had to
rename them all to begin with a period ".".
e.g
Maildir
Maildir/{cur,new,tmp}
Maildir/.account1/{cur,new,tmp}
Maildir/.account2/{cur,new,tmp}
Maildir/.account3/{cur,new,tmp}
etc
If I uninstall Courier and install dovecot, will these "period" dirs be
seen by default?
I am fairly new to this and
2009 May 04
0
[LLVMdev] [PATH] Fixes for the amd64 JIT code
Committed as revision 70929. Thanks.
Evan
On May 3, 2009, at 8:29 PM, vargaz wrote:
>
> Hi,
>
> If this looks ok, could somebody check it in ?
>
> thanks
>
> Zoltan
>
>
> Evan Cheng-2 wrote:
>>
>> Looks good. Thanks.
>>
>> Evan
>>
>> On May 1, 2009, at 8:40 AM, Zoltan Varga wrote:
>>
2007 May 03
2
Single Title for the Multiple plot page
Dear List,
In R we can plot multiple graphs in same page using
par(mfrow = c(*,*)). In each plot we can set title
using main and sub commands.
However, is there any way that we can place an
universal title above the set of plots placed in the
same page (not individual plot titles, all i need is a
title of the whole graph page) as well as sib-titles?
Do I need any package to do so?
Thank you
2007 Apr 14
1
how to simulate key_down event(when event.get_key_code()==Wx::K_DOWN) in ListCtrl or TreeCtrl?
I want to simulate vi(vim) like operations in ListCtrl or TreeCtrl,
that is, for example, when user pressed a ''j'' on keyboard,the selected
item change into the next one item, just like user press a
Wx::K_DOWN(arrow key down on keyboard) .
but not jump to some item started with a "J" charater.
evt_tree_key_down(TreeTest_Ctrl) { | e | on_tree_key_down(e) }
...
def
2016 Nov 23
2
RFC: code size reduction in X86 by replacing EVEX with VEX encoding
I would like a command line option to disable this optimization. That way
tests can still verify that EVEX instructions came out of isel by using
-show-mc-encoding.
On Wed, Nov 23, 2016 at 5:01 AM Hal Finkel via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
>
> ------------------------------
>
> *From: *"Gadi via llvm-dev Haber" <llvm-dev at lists.llvm.org>
>
2015 Aug 18
2
RFC for a design change in LoopStrengthReduce / ScalarEvolution
> Of course, and the point is that, for example, on x86_64, the zext here is free. I'm still trying to understand the problem...
>
> In the example you provided in your previous e-mail, we choose the solution:
>
> `GEP @Global, zext(V)` -> `GEP (@Global + zext VStart), {i64 0,+,1}`
> `V` -> `trunc({i64 0,+,1}) + VStart`
>
> instead of the actually-better
2018 Mar 28
4
x86 instruction format which takes a single 64-bit immediate
I am attempting to create an instruction which takes a single 64-bit
immediate. This doesn't seem like a thing that would exist already (because
who needs an instruction which just takes an immediate?) How might I
implement this easily? Perhaps I could use a format which encodes a
register, which is then unused?
Thanks for the help.
Gus
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2016 Nov 24
3
RFC: code size reduction in X86 by replacing EVEX with VEX encoding
> I would like a command line option to disable this optimization. That way tests can still verify that EVEX instructions came out of isel by using -show-mc-encoding.
I think that keeping tests compatibility is not a reason for an additional “llc” flag. We check encoding in test/MC/X86 dir.
Is there any option to report-out from llc in non-debug mode? It should be an option to control
2006 Aug 10
6
save without commit ?
How do I get ''save'' to execute without commit?
I have tried:
ActiveRecord::Base.connection.begin_db_transaction
# do some stuff that doesn''t issue a database COMMIT statement
# then:
@myObject.save
# this issues a COMMIT but it shouldn''t! Shouldn''t it wait until I''ve
called:
ActiveRecord::Base.connection.commit_db_transaction
?
what am
2013 Apr 11
2
Read the data from a text file and reshape the data
I have a data set for different time intervals. The data has three comment
lines before data for each time interval. For each time interval there are
500 data points. I want to change the dataset such that I have the following
format:
t1 t2 t3 ................
0.00208 0.00417 0.00625 .................
a1 a2 a3 ...................