Displaying 20 results from an estimated 1100 matches similar to: "Bug in SMBCLIENT"
2014 Aug 05
2
[LLVMdev] Warning about variable optimized away?
Hello,
it it possible to get a kind of diagnostics if the variable
is totally optimized away? For example, in:
void foo (struct some_type *obj) {
... some code where 'obj' is not used ...
bar (obj->some_member);
... some code where 'obj' is not used again ...
baz (obj->some_member);
}
'obj' is likely to be optimized away so only
2016 Feb 24
1
Publication : CERE LLVM Based Codelet Extractor and REplayer
Hello,
We have published two papers which build upon the LLVM
Compiler Infrastructure. Would it be possible to include them in the
LLVM related publications at http://llvm.org/pubs/ ?
I attach below
the bibliographic references:
"CERE: LLVM Based Codelet Extractor and
REplayer for Piecewise Benchmarking and Optimization"
P. de Oliveira
Castro, C. Akel, E. Petit, M. Popov, and W.
2018 Jan 30
0
Publication LLVM Related Publications Submission
Dear Mihail,
I've added these two publications to the publications page. Please
review it and let me know if I need to make any changes. In particular,
if you have URLs to use for the papers, having those would be greatly
appreciated.
Regards,
John Criswell
On 11/28/17 12:05 PM, Mihail Popov via llvm-dev wrote:
>
> Hello,
>
> I would like to submit two papers that use LLVM
2017 Nov 28
2
Publication LLVM Related Publications Submission
Hello,
I would like to submit two papers that use LLVM to the
Related Publications section.
Both papers focus on code isolation
applied to perform piecewise compiler optimizations.
The code isolation
process is performed by CERE, an open source tool based on LLVM.
The
second paper is an extended version of the first one.
1) Piecewise
Holistic Autotuning of Compiler and Runtime Parameters
2013 Dec 10
3
[LLVMdev] Summary of TableNextGen BOF
Hello everyone.
I apologise for the sizeable delay in sending this.
The BoF was attended by quite a lot of people and there was general
agreement that tablegen needs improvement in some shape of form. However
there are many divergent ideas as to how to go about this improvement. Of
course this is completely natural, tablegen being a versatile tool used by
many different people for many different
2005 Mar 05
4
how can I identify disconnect due to low <queue-size>
> On Sat, 2005-03-05 at 23:52, Mihail Egorov wrote:
> > 1. How can I identify disconnect due to low <queue-size>. Suppose, I
have
> > enabled loglevel=4 (debug). Suppose, I have network jam. What shall I
see at
> > error.log?
>
> There is a log message that signifies the removal of a listener for
> being too slow and that is
> "Client has fallen too far
2013 Dec 12
0
[LLVMdev] Summary of TableNextGen BOF
On Tue, Dec 10, 2013 at 6:38 AM, Mihail Popa <mihail.popa at gmail.com> wrote:
> Hello everyone.
>
> I apologise for the sizeable delay in sending this.
>
> The BoF was attended by quite a lot of people and there was general
> agreement that tablegen needs improvement in some shape of form. However
> there are many divergent ideas as to how to go about this improvement.
2013 Apr 08
1
[LLVMdev] Is r174746 broken on ARM?
On 04/04/2013 05:09 PM, Hal Finkel wrote:
> Looking briefly at the code in comment 5 of PR15581, is that the pre-decrement case?
> I can't test that case on PPC, so I can certainly believe that there is a problem somewhere.
> The relevant code is a little farther down:
>
> APInt OV =
> cast<ConstantSDNode>(Offset)->getAPIntValue();
> if (AM ==
2013 Apr 11
1
[LLVMdev] Is r174746 broken on ARM?
On 04/10/2013 10:22 PM, Hal Finkel wrote:
>> Okay, great! Can you please generate a test case? In case you don't
>> know, an easy way is this: place an assert that will crash the code
>> generation in the pre-dec case you've highlighted, then use bugpoint
>> to produce a reduced test case for the crash.
>
> [list not cc'd]
>
> Were you able to make
2013 Apr 04
0
[LLVMdev] Is r174746 broken on ARM?
----- Original Message -----
> From: "Dmitry Antipov" <antipov at dev.rtsoft.ru>
> To: "Hal Finkel" <hfinkel at anl.gov>
> Cc: "Renato Golin" <renato.golin at linaro.org>, llvmdev at cs.uiuc.edu
> Sent: Thursday, April 4, 2013 3:22:05 AM
> Subject: Is r174746 broken on ARM?
>
> Hello Hal,
>
> I have a strong suspicion
2009 Apr 20
1
Announcing our 2009 Google Summer of Code students
Congratulations to our 2009 Google Summer of Code Students:
Claudiu Mihail
Liu Aleaxander
Claudiu will work on CLI/parser migration to C, and Liu will work on
ext4 support and filesystem migration to C. In combination, this should
help get Syslinux into a much more portable state.
We're looking forward to your work!
-hpa
2013 Apr 08
1
[LLVMdev] [PATCH] Two patches related to ARM TrustZone support
Hi.
Please see attached for review two patches related to ARM TrustZone.
The first patch (LLVM-705.trustzone.patch) declares a new subtarget feature for TrustZone and adds it as requirement for the Secure Monitor Call instruction.
The second patch (LLVM-706.trustzone_cortex.patch) applies the newly created feature to the relevant processors.
Regards,
Mihai Popa
-- IMPORTANT NOTICE: The contents
2013 Jul 18
1
[LLVMdev] Trap instruction for ARMv7 and Thumb
HI group.
I was wondering why the "trap" instruction is implemented in the ARM
backend as an undefined opcode. For ARM mode, it uses 0xe7ffdefe, for
Thumb 0xdefe.
Why not use the BKT #imm instruction?
Does anybody remember the reason behind this?
Thanks,
Mihai
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2005 Feb 10
4
Could anybody kindly add statically linked icecast 2.2.0 download to www.icecast.org?
This is important to Debian users -- packets exists only for testing and
unstable version of Debian Linux.
2013 Apr 04
2
[LLVMdev] Is r174746 broken on ARM?
Hello Hal,
I have a strong suspicion that your constant folding optimization
introduced at r174746 is broken on ARM. There is a bug about it:
http://llvm.org/bugs/show_bug.cgi?id=15581
There is no such issue with 3.2, and reverting r174746 on top of
r178740 also fixes the problem. I'm trying to fix it myself, but
still have no good ideas; so it would be great to have an advice
from you.
2005 Mar 05
3
how can I identify disconnect due to low <queue-size>
1. How can I identify disconnect due to low <queue-size>. Suppose, I have
enabled loglevel=4 (debug). Suppose, I have network jam. What shall I see at
error.log?
2. Is it possible to mark reason of disconnect at standard access/error log
at level 2 (warn)?
That is, when disconnect is FORCED by server, this will be marked at level 2
(warn) or may be even 1(error).
2013 Apr 30
3
[LLVMdev] A simpler method to reject undefined encodings
Hello.
Sometimes the constraints imposed on an instruction's encoding are too
complex to be described in tablegen alone. In such cases a custom decoder
method is implemented. This makes sense when the decoding itself is very
complex, but it is wasteful to do it only when checking
additional constraints. This is because:
1. a custom decoder method has to decode operands, set opcodes, etc. -
2010 Jun 13
2
wrappers
Hi,
I've sent one of these before, but i wasn't subscribed, and i'm unsure if it
went out. I'm subscribed now and i've written another (i believe) nifty wrapper
for oggz-tools.
oggz-comments - allows a user to pass the plain text file with each tag on their
own line
theoracomment - works like 'vorbiscomment' from VorbisTools package, but sets
comments for the
2014 May 13
2
[LLVMdev] Instructions with overlapping encodings that are disambiguated by field comparisons
Hi,
I'm not sure how to handle some of the trickier instruction encodings in MIPS64r6. My problem is that some instructions determine the operation based on the relationship between two fields. For example, 'beqc $rs, $rt, offset' (branch if equal, no delay slot) and bovc (branch if addition would overflow, no delay slot) share the same major opcode and field layout. When the register
2013 May 01
0
[LLVMdev] A simpler method to reject undefined encodings
Hi Mihail,
> static DecodeStatus CheckNEONConstraint(const MCInst &Inst, unsigned Insn)
[...]
> ConstraintCheckMethod = "CheckNEONConstraint"
In general I like the idea of an instruction-validation method. I
think it could also potentially solve the SoftFail/UNPREDICTABLE
issues that are looming (and partially resolved for decoding at
present).
However, I think that to cope