Displaying 20 results from an estimated 3000 matches similar to: "connecton reset by peer - socket problem"
2025 Feb 12
1
how to make syslinux wait till all libs are loaded over slow tftp connecton
On Wed, Feb 12, 2025 at 01:57:53AM +0100, Jelle de Jong via Syslinux
wrote:
> Hello everybody,
>
> I got a slow TFTP upload over TINC-VPN and Starlink,technically it all works
> however syslinux is giving me timeout as unable to locate configuration file
> or boot:
>
> It does not wait till default or menu.c32 is fully loaded to the client.
Hi Jelle,
I don't think the
2025 Feb 12
1
how to make syslinux wait till all libs are loaded over slow tftp connecton
Hello everybody,
I got a slow TFTP upload over TINC-VPN and Starlink,technically it all
works however syslinux is giving me timeout as unable to locate
configuration file or boot:
It does not wait till default or menu.c32 is fully loaded to the client.
Thank you in advance,
Jelle de Jong
Feb 12 01:50:14 firewall01 dnsmasq-tftp[841146]: sent
/srv/tftp/bios/lpxelinux.0 to 192.168.26.164
Feb
2006 Dec 15
1
catching DNAT''ed packet
Hi.
I have a Server''s network with some servers in it, all with
192.168.1.0/25 ips. There is also a router in that network with ip
192.168.1.1. This router also connected to a client''s network
10.10.0.0/16 with ip 10.10.100.1.
All services on each server are given their virtual address from one of
two virtual networks 192.168.1.128/28 and 192.168.1.144/28.
192.168.1.128/28 is
2012 Oct 04
3
(no subject)
Hi
I would like to learn how the R function "hclust" deals with ties. It is
written in Fortran, so I cannot access the code. Thanks!!
[[alternative HTML version deleted]]
2011 Mar 16
5
Xen and the InfiniBand
Hi, all,
Is the Xen currently compatible with the InfiniBand? I found some
information about the Smart I/O module, but it was posted in 2006. Is the
module still maintained? Or, are there any up-to-date alternatives for
that?
Many thanks,
Chiu
_______________________________________________
Xen-users mailing list
Xen-users@lists.xensource.com
http://lists.xensource.com/xen-users
2016 Dec 12
2
[PATCH] drm/nouveau: fix unknown chipset for GTX 1060
Nouveau driver shows unknown chipset (136000a1) for GTX 1060, so it
only gives VGA resolution on screen. Use the same chipset as nv134
then it shows FullHD. This commit copies fields from nv134_chipset
to nv136_chipset for GTX 1060.
Signed-off-by: Chris Chiu <chiu at endlessm.com>
---
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 29 +++++++++++++++++++++++
1 file changed, 29
2017 Jun 02
3
Kernel panic on nouveau during boot on NVIDIA NV118 (GM108)
We are working with new desktop that have the NVIDIA NV118
chipset.
During boot, the display becomes unusable at the point where the
nouveau driver loads. We have reproduced on 4.8, 4.11 and linux
master (4.12-rc3).
Dmesg log is attached.
Is this a known issue? Anything we can do to help?
Thanks
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2017 Feb 14
1
[PATCH] drm/nouveau/core: recognise GP107 chipset
From: Chris Chiu <chiu at endlessm.com>
This new graphics card was failing to initialize with nouveau due to
an "unknown chipset" error.
Copy the GP106 configuration and rename for GP107/NV137. We don't
know for certain that this is fully correct, but brief desktop testing
suggests this is working fine.
Signed-off-by: Chris Chiu <chiu at endlessm.com>
Signed-off-by:
2005 Sep 22
3
[LLVMdev] name collision - llvm::tie and boost::tie
The BGL (Boost Graph Library) defines tie(), which is exactly what the
tie() defined in STLExtras.h.
The header files of GBL use boost::tie(), and other boost libraries
use boost::tie() too.
How to resolve the ambiguity for compiler?
--
Tzu-Chien Chiu,
3D Graphics Hardware Architect
<URL:http://www.csie.nctu.edu.tw/~jwchiu>
2011 May 09
6
SLES 11 SP1 Client rpms built but not working
Hi all,
I used the method described below to build client rpms with the source kit lustre-1.8.5.tar.gz.
There was only one error reported during the make rpms, relating to lustre-iolit-1.2-root,
but the rpms were built under /usr/src/packages/RPMS/x86_64.
The rpms lustre-modules, lustre and lustre-tests were then installed smoothly without any complaints.
But the subsequent "modprobe
2011 Aug 10
1
subqueries in sqlQuery function (package RODBC)
Hi R users.
sorry for missing example and if question is to general but I am wondering
if it is possible to execute subqueries in function sqlQuery (package RODBC)
with opened connection with Excel or SQL server 2000. I couldn't find any
example of this.
And if it is possible what should be a correct syntax for this query:
SELECT ct,COUNT(*) as n
FROM (SELECT COUNT(*) AS ct FROM children
2005 Mar 29
2
Nicecast
So I just setup my Icecast server on my unix box but I am having trouble
with Nicecast in trying to send a stream to it. Nicecast connects to the
server fine when I leave the mountpoint setting blank but when I put
something in there, it fails to login. Regardless, neither alternative
produces a working stream. Although, when I don?t enter a mountpoint and the
broadcast is playing, my icecast
2005 Sep 07
4
[LLVMdev] LiveIntervals, replace register with representative register?
I don't understand the following code snippet in LiveIntervalAnalysis.cpp.
Why changing the type of the opreand from a virtual register to a
machine register? The register number (reg) is still a virtual
register index (>1024).
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
// perform a final pass over the instructions and compute spill
// weights, coalesce
2005 Jul 27
3
[LLVMdev] How to define complicated instruction in TableGen (Direct3D shader instruction)
Each register is a 4-component (namely, r, g, b, a) vector register.
They are actually defined as llvm packed [4xfloat].
The instruction:
add_sat r0.a, r1_bias.xxyy, r3_x2.zzzz
Explaination:
'.a' is a writemask. only the specified component will be update
'.xxyy' and '.zzzz' are swizzle masks, specify the component
permutation, simliar to the Intel SSE permutation
2005 Apr 24
4
[LLVMdev] trig language-like code generator generator
i'd like to know if there is any plan or existing work to add a Aho's
trig language like code generator generator?
"...If you are starting a new port, we recommend that you write the
instruction selector using the SelectionDAG infrastructure."
any other things i should know before i write one?
thank you.
2005 Apr 24
2
[LLVMdev] trig language-like code generator generator
http://portal.acm.org/citation.cfm?id=75700
On 4/25/05, Chris Lattner <sabre at nondot.org> wrote:
> On Sun, 24 Apr 2005, Tzu-Chien Chiu wrote:
> > i'd like to know if there is any plan or existing work to add a Aho's
> > trig language like code generator generator?
>
> Trig is a code generator generator? Is there any documentation for it
> available
2005 Sep 07
3
[LLVMdev] LiveIntervals invalidates LiveVariables?
I though LiveVariables may be invalidated by LiveIntervals, but it's
declared not:
void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
{
AU.addPreserved<LiveVariables>();
AU.addRequired<LiveVariables>();
...
LiveInterval may coalesce virtual registers and remove identity moves
instructions:
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
2005 Jul 23
3
[LLVMdev] How to partition registers into different RegisterClass?
2005/7/23, Chris Lattner <sabre at nondot.org>:
>
> What does a 'read only' register mean? Is it a constant (e.g. returns
> 1.0)? Otherwise, how can it be a useful value?
Yes, it's a constant register.
Because the instruction cannot contain an immediate value, a constant
value may be stored in a constant register, and it's defined _before_
the program starts by
2005 Dec 13
3
[LLVMdev] The live interval of write-only registers
In my ISA, some registers are write-only. These registers serve as
output ports, writing to these registers will output the values to an
external device. They cannot be read. So their live intervals should
not be joined with any other registers.
The only way I know to do this is defining several instruction
'templates' for an opcode (of course automatically generated by a
script) similar
2005 May 10
3
[LLVMdev] llvm fits in the national compiler infrastructure (nci)?
national compiler infrastructure - http://www.cs.virginia.edu/nci/
is there any on-going efforts to integrate llvm with other nci projects?