similar to: [Xen-devel] Crash during boot in Debian lenny default dom0 kernel (2.6.26-2-xen-686) / bugfix patch

Hello, The email (thread) below from xen-devel mailinglist indicates the changesets that should fix the bug that causes the lenny 2.6.26 xen kernel to crash on newer xen hypervisors. The workaround for this bug has been to use pci=nomsi on the dom0 kernel cmdline, but it would be better to apply the actual fix to the xen kernel in lenny. More information on xen-devel (archives). -- Pasi

With the .end() accessor having become optional and noting that several of the accessors'' behavior really depends on the result of msi_maskable_irq(), the splits the MSI IRQ chip type into two - one for the maskable ones, and the other for the (MSI only) non-maskable ones. At once the implementation of those methods gets moved from io_apic.c to msi.c. Signed-off-by: Jan Beulich

The i915 driver probes chip version through PCH ISA bridge device / vendor ID. Previously, the PCH ISA bridge is exposed as PCI-PCI bridge in qemu-xen-trad, which breaks the assumption of the driver. This change fixes the issue by correctly exposing the ISA bridge to domU. Signed-off-by: Rui Guo <firemeteor@users.sourceforge.net> Tested-by: Rui Guo <firemeteor@users.sourceforge.net>

Several of these messages we coded using line continuation within a string literal. This is generally not recommended and also lead to odd sequences of many blanks in the middle of the messages. The message indicating a discarded write due to MSI-X already being enabled doesn''t need to be issued when a write doesn''t actually modify the current value. Adjust the surrounding logic

For assigned devices, use common code to enable msi-x. We need a special "assigned" option as assigned devices lack a standard way to get vector usage. Signed-off-by: Michael S. Tsirkin <mst at redhat.com> --- hw/device-assignment.c | 329 ++++++++++++------------------------------------ hw/device-assignment.h | 7 +- hw/msix.c | 9 ++- hw/pci.h

For assigned devices, use common code to enable msi-x. We need a special "assigned" option as assigned devices lack a standard way to get vector usage. Signed-off-by: Michael S. Tsirkin <mst at redhat.com> --- hw/device-assignment.c | 329 ++++++++++++------------------------------------ hw/device-assignment.h | 7 +- hw/msix.c | 9 ++- hw/pci.h

For assigned devices, use common code to enable msi-x. Add "hack" option as assigned devices lack a standard way to get vector usage. Signed-off-by: Michael S. Tsirkin <mst at redhat.com> --- hw/device-assignment.c | 336 ++++++++++++------------------------------------ hw/device-assignment.h | 8 +- hw/msix.c | 11 ++- hw/pci.h | 4 + 4 files

For assigned devices, use common code to enable msi-x. Add "hack" option as assigned devices lack a standard way to get vector usage. Signed-off-by: Michael S. Tsirkin <mst at redhat.com> --- hw/device-assignment.c | 336 ++++++++++++------------------------------------ hw/device-assignment.h | 8 +- hw/msix.c | 11 ++- hw/pci.h | 4 + 4 files

The IRQ handling code requires pcidevs_lock to be held only for MSI interrupts. As the handling of which was now fully moved into msi.c (i.e. while applying fine without, the patch needs to be applied after the one titled "x86: split MSI IRQ chip"), io_apic.c now also doesn''t need to include PCI headers anymore. Signed-off-by: Jan Beulich <jbeulich@suse.com> ---

PCI devices save the msi and msix capability offset in pci_dev->msi_cap and pci_dev->msix_cap. When we access PCI device MSI and MSIX registers, we can use msi_cap and msix_cap in pci_dev directly. Remove the pos member in msi_attrib. Signed-off-by: Yijing Wang <wangyijing at huawei.com> --- arch/mips/pci/msi-octeon.c | 4 ++-- drivers/pci/host/pcie-designware.c | 2 +-

Accelerated msix entry is initialized to zero when msixtbl_pt_register is called. This doesn''t match the value from qemu side, although pirq may already be mapped and binded in qemu side. Kernel will get wrong value when reading msix info. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@oracle.com> Tested-by: Yuval Shaia <yuval.shaia@oracle.com> --- tools/libxc/xc_domain.c

Looking at the MSI implementation I have a couple of questions: 1) There currently seems to be a hidden requirement of NR_PIRQS in the kernel needing to be no smaller than NR_IRQS in the hypervisor. Otherwise, the pirq returned from PHYSDEVOP_map_pirq may collide with the dynamic IRQs in the kernel or even be out of range altogether. Therefore I think that NR_PIRQS has to become a variable

wasm-ld is currently unable to link a shared wasm library (generated with `wasm-ld --shared`) with .o files and produce a working executable. I'm curious if there's a fundamental reason for this, or is this simply something that wasn't needed and could be implemented if needed. I think this could be done by - Resolving "GOT.mem" and "GOT.func" imports and

MSI interrupt will not only used in PCI device, more and more Non-PCI device also want to use MSI. ARM GIC v3 spec says in ARM platform with GIC v3 controller, Non-PCI device can also be design to support MSI to simplify interrupt wires, for the existing Non-PCI device, consolidator is designed and used to translate legacy interrupt to MSI. So for support Non-PCI MSI device, generic MSI driver is

Support PV on HVM MSIX remapping The technique is the same used with MSI: if the guest enables an MSIX passing 0 as vector number, then read the address and use it as pirq number for the following mapping request to Xen. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> diff --git a/hw/pt-msi.c b/hw/pt-msi.c index f0fb3e3..b01744e 100644 --- a/hw/pt-msi.c +++

lspci shows MSI enabled for PCI device. PCI passthrough works fine. However, as soon as the MSI driver for card is insmodded, kernel panics. This is on xen-unstable. Tried the same with xen-3.3.0 which is supposed to have MSI passthrough, but the same guest shows MSI as disabled. Any else seen this bug, or know of a workaround ? Trace is as follows : ------------[ cut here ]------------

> -----Original Message----- > From: linux-pci-owner at vger.kernel.org [mailto:linux-pci-owner at vger.kernel.org] > On Behalf Of Yijing Wang > Sent: Saturday, July 26, 2014 8:39 AM > To: linux-kernel at vger.kernel.org > Cc: Xinwei Hu; Wuyun; Bjorn Helgaas; linux-pci at vger.kernel.org; > Paul.Mundt at huawei.com; James E.J. Bottomley; Marc Zyngier; linux-arm- > kernel at

> -----Original Message----- > From: linux-pci-owner at vger.kernel.org [mailto:linux-pci-owner at vger.kernel.org] > On Behalf Of Yijing Wang > Sent: Saturday, July 26, 2014 8:39 AM > To: linux-kernel at vger.kernel.org > Cc: Xinwei Hu; Wuyun; Bjorn Helgaas; linux-pci at vger.kernel.org; > Paul.Mundt at huawei.com; James E.J. Bottomley; Marc Zyngier; linux-arm- > kernel at

On 2014/7/4 11:30, Ilia Mirkin wrote: > On Thu, Jul 3, 2014 at 11:09 PM, Yijing Wang <wangyijing at huawei.com> wrote: >> On 2014/7/4 10:43, Ilia Mirkin wrote: >>> On Thu, Jul 3, 2014 at 10:35 PM, Yijing Wang <wangyijing at huawei.com> wrote: >>>> Hi Brian, >>>> From your 01:00.0 VGA compatible controller PCI config register, it supports 1

This patch enables PCI passthrough with stub domain. PCI passthrough with stub domain has failed in the past. The primary reason is that hypercalls from qemu in stub domain are rejected. This patch allows qemu in stub domain to call the hypercalls which is needed for PCI passthrough. For security, if target domain of hypercall is different from that of stub domain, it rejects hypercall. To use