similar to: Is this a DDoS to reach Asterisk?

Hi, there I am writing an backend, and I met a problem. We don't have load/store instructions for vector predicate registers(vpr for short). The hardware has 64 vector registers(vr for short) and 8 vector predicate registers. And there is no move instructions between vr and vpr. vr supports many operations, and vpr supports vpror, vprxor, vprand and vprinv operations. A vr has 512 bits, and

Hi, I am planning to expanding the pseudo instructions in XXXTargetLowering::EmitInstrWithCustomInserter(), and use temporary virtual registers as operands. If I use virtual registers, do I need to mark them as "early clobber"? I saw that sometimes they marked virtual register as "early clobber" in EmitInstrWithCustomInserter() in MIPS backend. What is the effect of marking a

Hi All, I *think* it's ddply because the function recognizes vr1, etc, in other parts of the function. Here's some code: # create dataset PROV.PM.FBCTS <- c(0.00 ,0.00, 33205.19, 25994.56, 23351.37, 26959.56 ,27632.58, 26076.24, 0.00, 0.00 , 6741.42, 18665.09 ,18129.59 ,21468.39 ,21294.60 ,22764.82, 26076.73) FBCTS.INV.TOT <- c(0 , 0, 958612, 487990, 413344, 573347,

I have a question about how to reference variables in a dataframe. Normally, after I have read in some Stata data using the following command all <- read.dta('all.dta') Whenever I want to use the variable "sat.vr1" in the "all" data frame, I do so using all$sat.vr1 However, I'd like to be able to use the sat.vr1 variable without the "all$" (as well

Hi. If I have a vector, v_1, and another vector of positive integers, i_1, the same length as v_1, then rep(v_1,i_1) will repeat v_i[j] exactly i_1[j] times, like so: >rep(c(1,2,3),c(3,2,1)) [1] 1 1 1 2 2 3 > I'd like to do the same sort of thing where I replace v_1 with a matrix, and the jth row of the matrix is repeated i_1 times. Obviously, I could do this with for loops, like

On May 9, 2013, at 3:05 PM, Jeff Bush <jeffbush001 at gmail.com> wrote: > On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: >> Jeff Bush <jeffbush001 at gmail.com> writes: >> >>> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >>> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >>> %sum = fadd %tx, %ty >>> %newvalue

Hi all, I'm trying to create a new volume in a netfs pool. The pool works correctly and it is active. If I try to create the volume from the virt-manager GUI nothing happens. While if I use virsh this is the result. *virsh # pool-list * *Name State Autostart * *-----------------------------------------* *routers active yes * * * *virsh #

Hi all, Can anyone give an idea to solve my problem? I'm implementing backend part using LLVM for my research architecture. The main issue is that this architecture cannot use stack/heap. So, all the value should be stored in the register. Given that architecture, load/store instruction in IR uses virtual register to load/ store the value. For example: C source code is: if(...) { a = 1;

On Wed, Aug 07, 2013 at 08:04:13PM -0700, Sudeep Dutt wrote: > From: Caz Yokoyama <Caz.Yokoyama at intel.com> > > This patch introduces a sample user space daemon which > implements the virtio device backends on the host. The daemon > creates/removes/configures virtio device backends by communicating with > the Intel MIC Host Driver. The virtio devices currently supported

On Wed, Aug 07, 2013 at 08:04:13PM -0700, Sudeep Dutt wrote: > From: Caz Yokoyama <Caz.Yokoyama at intel.com> > > This patch introduces a sample user space daemon which > implements the virtio device backends on the host. The daemon > creates/removes/configures virtio device backends by communicating with > the Intel MIC Host Driver. The virtio devices currently supported

Endianness issues are now consistent as per the documentation in host/mic_virtio.h. Note that the host can be both BE or LE whereas the card is always LE. Memory space sparse warnings are fixed for now by using __force. This is sufficient for now since the driver depends on x86 but will need to be revisited if we support other architectures which treat I/O memory differently from system memory.

Endianness issues are now consistent as per the documentation in host/mic_virtio.h. Note that the host can be both BE or LE whereas the card is always LE. Memory space sparse warnings are fixed for now by using __force. This is sufficient for now since the driver depends on x86 but will need to be revisited if we support other architectures which treat I/O memory differently from system memory.

Ah, I think I get it now. This was mentioned earlier in the thread, but it didn't click at the time. It sounds like I can do instruction selection with a pattern like (omitting selection of the sources): let Constraints = "$dst = $oldvalue" in { def MASKEDARITH : MyInstruction< (outs VectorReg:$dst), (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2,

On Dec 2, 2011, at 12:40 PM, Evan Cheng wrote: > There have been quite a bit of discussions about adding machine instruction bundle to support VLIW targets. I have been pondering what the right representation should be and what kind of impact it might have on the LLVM code generator. I believe I have a fairly good plan now and would like to share with the LLVM community. Let me add some

Hi,   For a custom target, there is a pass to perform memory dependence analysis, where, i need to get memory pointer for "load instruction". I want to check the pointer alias behavior. I am getting this by considering the memoperands for the load instruction.   For "load instruction", Machine Instruction dumps as below:   vr12<def> = LD_Iri %vr2<kill>, 0;

. and yes, one more thing. On some architectures it might be desirable to know the _order_ of instructions in the packet. That is a bit trickier.. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Friday, December 02, 2011 2:40 PM To: LLVM Dev Subject: [LLVMdev]

These patches fix various issues which were reported or found with the MIC driver. Changelog ========= v2 => v3: * Reorder patch 5 in v2 to patch 4 in v3. * Split patch 4 in v2 into patches 5 and 6 in v3. v1 => v2: @ https://lkml.org/lkml/2013/11/26/376 * Address review comments @ https://lkml.org/lkml/2013/11/26/443 in patch 5. v1: Initial post @ https://lkml.org/lkml/2013/11/26/321

These patches fix various issues which were reported or found with the MIC driver. Changelog ========= v2 => v3: * Reorder patch 5 in v2 to patch 4 in v3. * Split patch 4 in v2 into patches 5 and 6 in v3. v1 => v2: @ https://lkml.org/lkml/2013/11/26/376 * Address review comments @ https://lkml.org/lkml/2013/11/26/443 in patch 5. v1: Initial post @ https://lkml.org/lkml/2013/11/26/321

These patches fix various issues which were reported or found with the MIC driver. Ashutosh Dixit (3): misc: mic: Bug fix for sysfs poll usage. misc: mic: Fix sparse warnings and other endianness issues. misc: mic: Fix user space namespace pollution from mic_common.h. Sudeep Dutt (2): misc: mic: Change mic_notify(...) to return true. misc: mic: Minor bug fix in 'retry' loops.

These patches fix various issues which were reported or found with the MIC driver. Ashutosh Dixit (3): misc: mic: Bug fix for sysfs poll usage. misc: mic: Fix sparse warnings and other endianness issues. misc: mic: Fix user space namespace pollution from mic_common.h. Sudeep Dutt (2): misc: mic: Change mic_notify(...) to return true. misc: mic: Minor bug fix in 'retry' loops.