similar to: Deadlock in Asterisk 1.4.29.1

Displaying 20 results from an estimated 400 matches similar to: "Deadlock in Asterisk 1.4.29.1"

2010 Mar 03
6
Identify scripts connecting to the asterisk manager
Is there any easy way to identify which script or service is connecting to the Asterisk manager? Somewhere on my system a script or service is trying to connect with a bad user name or password. I get the following error: connect attempt from '127.0.0.1' unable to authenticate I thought maybe I could do a tcpdump on port 5038 and try to fish out the bad username or password but I
2010 Mar 02
5
MWI and 1.6.1
We are having an issue with Asterisk 1.6.1 and the MWI turning on when a user doesn't have voicemail. We see random MWI lights come on and the phone indicates a random number of messages (its been anywhere from 1-14) when a server reload is done. I just checked one user, they have no messages old or new and the phone (Polycom IP330) indicates that they have 2 messages. The user will check for
2010 Apr 30
2
B400P card crashes conncection
Hi, I have a B400P BRI card with point-to-point connection (signalling: bri_cpe) with this dmesg: http://pastebin.com/sXrRt1yM When i restart asterisk server, the card cannot connect to the telco, the control led flashes red. If I unplug the cable between the ISDN nt and the card and wait 40 sec, the card can connect and works properly. The telco says the asterisk crashes the connection
2017 Sep 04
7
Reaching definitions on Machine IR post register allocation
Hi, Just to clarify I am looking for a whole machine function analysis not just something restricted to within a machine basic block. Thanks. Regards, Venu. From: Raghavan, Venugopal Sent: Saturday, September 02, 2017 12:56 PM To: llvm-dev at lists.llvm.org Subject: Reaching definitions on Machine IR post register allocation Hi, Given a definition of a register by a machine instruction in
2017 Jul 31
1
LLVM's loop strength reduction module
Hi, Sorry I took a long time to reply as it took me some time to get some understanding of the code even to ask some specific questions (I have a test case in which LSR does not kick in and wanted to understand the code to figure out why it was not kicking in). Here are some specific questions I have: 1) It appears that LSR works only for the inner-most loop. Is this correct? Can you tell
2017 Jul 06
3
LLVM's loop strength reduction module
Hi Raghavan, I concur no specific docs. What do you want to know specifically? Cheers, -Quentin > On Jul 5, 2017, at 11:16 PM, Madhur Amilkanthwar via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > AFAIK, no official doc. > You can probably get better help if you ask specific questions (which part of the code you don't understand). > > On Thu, Jul 6, 2017 at 9:53
2020 Apr 08
3
Error with perf2bolt in LLVM BOLT
Hi, I was interested in trying out LLVM BOLT and generated profile data using Linux perf using the following: perf record -e cycles:u -o perf.data <command> This is without the use of LBR so I understand the performance improvements may not be much but this was more for becoming familiar with BOLT's commands. I then run: perf2bolt -nl -p perf.data -o perf.fdata <binary> and I
2017 Sep 12
6
Reaching definitions on Machine IR post register allocation
Hi Venu, > On Sep 11, 2017, at 11:00 PM, Raghavan, Venugopal via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi Krzysztof, > > Thanks for your reply. > > I agree that adding extra register units for x86 would be the right way to fix this. Do you know if there is a plan to fix this? No concrete plan, no. We've been thinking about for quite some time now, but
2017 Nov 24
2
Reaching definitions on Machine IR post register allocation
Hi Krzysztof, In one of your earlier emails in this thread you mentioned that you had some changes which add extra aliases for subregisters. Did you mean for X86? And is it extra register units that you added or aliases? I tried adding extra register units for X86 through some changes in CodeGenRegisters.cpp in TableGen but I am seeing a runtime error in one of my test cases possibly due to the
2010 Feb 17
2
asterisk dahdi fax problem
Hi, I run into a problem and I'm not shure what do I misconfigure. I've a B410P ISDN card with bri_cpe signalling and two Openvox (A1200, A800) cards with fxo_ks signalling, all with dahdi drivers. I can receive fax from a public number, but I can't send fax. The CLI says it picks up the line but no dialing. I tried the extension with an analog phone, it works fine, I can dial
2010 Apr 29
1
incoming call should ring on several dahdi channels
Hi, I need a feature from asterisk with dahdi channels, if there is an incoming call, it should ring on several dahdi channels. My channels look like: OFFICE1=DAHDI/13,,rtT OFFICE2=DAHDI/14,,rtT If I add this line: exten => 12345678,1,Dial(${OFFICE1}&{OFFICE2}) only OFFICE1 rings. If I change it to exten => 12345678,1,Dial(DAHDI/13&DAHDI/14) DAHDI/13 and 14 rings together,
2017 Nov 01
2
Reaching definitions on Machine IR post register allocation
Hi Geoff/Krzyssztof, Wouldn't the isRenamable() change be required even for the RDF based copy propagation? Maybe Hexagon does not impose ABI/ISA restrictions which require specific registers to be used in specific contexts. Also, if Geoff's copy propagation pass is invoked post-RA wouldn't it need to handle the x86 ISA feature which allows 8 bit/16 bit values to be moved into a
2009 Aug 25
14
3.4-testing : Kernel panic on bootup (mount: could not find filesystem /dev/root/)
Hi, I installed XEN 3.4-testing version without much problems in CentOS 5.3 running on quadcore Intel Nahelam processors using the following installation steps (as in the README) : <steps> hg clone http://xenbits.xensource.com/xen-3.4-testing.hg` cd xen-unstable.hg make world make install make linux-2.6-xen-config CONFIGMODE=menuconfig make linux-2.6-xen-build make linux-2.6-xen-install
2017 Oct 31
2
Reaching definitions on Machine IR post register allocation
Hi Venu, FWIW, I have a pass that does copy propagation after RA [1] (currently only within a basic block) that should be enabled some time in the not-too-distant future. It has been reviewed and accepted, but I'm currently working on getting a slight change to the MachineOperand representation [2] that should make the copy propagation change much simpler. I believe this change to
2017 Nov 13
2
Reaching definitions on Machine IR post register allocation
Hi Venu, This is happening because there is an implicit def of ECX on the COPY instruction. This was an issue on Hexagon as well. Let me give you some background. There are two kinds of implicit defs (and implicit uses, but I'll refer only to defs for brevity): (1) Those that indicate that some physical register (that is not an operand) is modified by a given instruction (EFLAGS is a good
2017 Jul 06
2
LLVM's loop strength reduction module
Hi, My name is Venugopal Raghavan and I work in AMD. I was trying to understand the code in the file LoopStrengthReduce.cpp but I am making very slow progress. Is there any additional documentation available that would help me understand the code, like a PPT presentation or a design document or maybe a paper? I did not find anything on the Internet. There are comments interspersed in the code
2017 Dec 19
4
MemorySSA question
Hi, I am new to MemorySSA and wanted to understand its capabilities. Hence I wrote the following program (test.c): int N; void test(int *restrict a, int *restrict b, int *restrict c, int *restrict d, int *restrict e) { int i; for (i = 0; i < N; i = i + 5) { a[i] = b[i] + c[i]; } for (i = 0; i < N - 5; i = i + 5) { e[i] = a[i] * d[i]; } } I compiled this program using
2017 Dec 19
2
MemorySSA question
On Tue, Dec 19, 2017 at 9:10 AM, Siddharth Bhat via llvm-dev < llvm-dev at lists.llvm.org> wrote: > I could be entirely wrong, but from my understanding of memorySSA, each > def defines an "abstract heap state" which has the coarsest possible > definition - any write will be modelled as a "new heap state". > This is true for def-def relationships, but
2009 Feb 16
3
Finishing up the contributors list as well
Guys, OK, now that we have the new core contributors squared away, we can go back to finishing the contributors list. There were some people who got added and then there is existing contributors list. I think Darren''s suggestion to wait to add new core contributors is fine (let the new constitution settle down and we can in the meanwhile have a more inclusive look at both rather than
2007 Nov 22
8
Link Properties text
Following is a short description on assigning priorities to a link (via dladm). Flows will have a similar mechanism (via flowadm). thanks, -venu ---------------------------------------------------------------------------- The components associated with a link or flow, such as Soft Ring Sets, Soft Rings and squeues, have kernel threads processing inbound/outbound packets. The scheduler