similar to: IAX2 NAT issues

Apart from religious grounds (!), is there any pros or cons why I should choose one over the other for a new install of asterisk ? Julian

Priorityjumping is totally ignored by my asterisk (tested 1.4.4 and 1.4.7.1 on FreeBSD 6.2) [general] priorityjumping=yes With n+101: exten => 1337,1,Dial(SIP/zytek,5,Ttj) exten => 1337,102,Dial(SIP/zytek,${RINGTIME},${OPTIONS}) exten => 1337,n,Hangup -- Executing [1337 at firma:1] Dial("SIP/113-087a3000", "SIP/zytek|5|Ttj") in new stack -- Called zytek

Hello, this isn't an Asterisk specific problem but I don't know who else to ask for help. This is my setup, it oftens finds double NAT situations: [Asterisk box] <-> [Firewall IPCop] <-INTERNET-> [Random Router] <-> [Softphone] In certain situations, when two or more client softphones use the port 5060 at the same time and try to register, the UDP translation state of

This series adds support for GM20B PLL's Maxwell features, namely glitchless switch and (more importantly) DFS support. DFS lets the PLL lower its output speed according to input current variations, making the clock more stable and allowing it to run safely at lower voltage. All GM20B additions are done in the last patch, which consequently ends up being considerably big ; fortunately, it

Hi all, i have a problem with 2 peers conecting to an asterisk machine, both are conected behind nat without any port mapping in the router, and the * is conected behind other nat with the port 4569 mapped to it address, the problem is: when a peer register to the asterisk the other cant register and viceversa, only gets registration the first one, im using firefly and a hardphone from wuchuan,

Following a series of patches to improve nouveaus clock tree parsing. Reclocking these engines (all but memory) is pretty stable on the cards I've tested. Please review and merge when approved. These patches do not solve the problem that core/shader engine doesn't like to be clocked up too far without fb following, with visible corruption as a result. I suspect this problem is unrelated

Hi people, i have problem with IAX2 between two asterisk PBX. When i try call some number i get "INVAL" packet, but when i try call same number via OpenVPN (is between this two asterisk) call is working fine.So i debug communications and here is my opinion ... Schema of connection: Asterisk1 -> ADSL router with NAT -> INTERNET -> Asterisk2 A)Calling directly via public

this is my first patch on the list through git send-mail and I hope everything is set up right, sorry for the noise here, but I don't want to try with an empty mail :) as the subject already says, this patch fixes one of the more serious issues while reclocking gddr5 on kepler cards. It works for me and for a bunch of others I met on IRC. Karol Herbst (1): pll/gk104: fix PLL instability

This series does some refactoring in the GK20A's volt and clk drivers (fixing a few things while we are at it) to let GM20B benefit from the GK20A's logic with which it is compatible. GM20B is capable of more sophisticated (and power-efficient) reclocking which will follow later. Even after this more fancy reclocking is merged, the present logic will remain used in the lowest speedo of

Hi Everyone, Just trying to connect the Zoiper Communicator to connect to Asterisk which is behind Pfsense. Here is what I get at debug and it doesn't register. Error code 16. Can someone please let me know their firewall, NAT, outbound 1-to-1 pfsense settings as it seems to me I am doing something wrong on the firewall? *Rx-Frame Retry[ No] -- OSeqno: 000 ISeqno: 000 Type: IAX

The situation is one of my asterisk servers is behind a NAT firewall and one is not. Both servers have multiple IAX peers. The NAT firewall has port 4569 mapped through to the asterisk server behind. But, the natted server is almost permanently unreachable from this non-natted server, even though, the non-natted server is almost permanently _reachable_ from the natted server. Details are below

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but

Fixes regression introduced in commit 70790f4f "drm/nouveau/clock: pull in the implementation from all over the place" When code was moved from nv50_crtc_set_clock to nvc0_clock_pll_set, the PLLs it is used for got limited to only the first two VPLLs. nv50_crtc_set_clock was only called to change VPLLs, so it didn't limit what it was used for in any way. Since nvc0_clock_pll_set is

http://bugs.freedesktop.org/show_bug.cgi?id=24668 Summary: KMS does not work with nva8 Product: xorg Version: unspecified Platform: Other OS/Version: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau AssignedTo: nouveau at lists.freedesktop.org ReportedBy:

In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch aims to suppress 29 missing-break-in-switch false positives. Addresses-Coverity-ID: 1456891 ("Missing break in switch") Addresses-Coverity-ID: 1324063 ("Missing break in switch") Addresses-Coverity-ID: 1324063 ("Missing break in switch")

Reclocking of NVAA/NVAC is substantially different from NV50+, enough to justify a separate clock implementation. This code is a forward-port of reclocking code that has been sitting in a branch for a while, and has been tested on my NVAC. Traces show no significant reasons why this shouldn't work on NVAA, but testers are always welcome. And since these are IGPs without dedicated RAM to

From: Steve Underwood <steveu at coppice.org> > It seems some cards use a PLL for their ADC, so they can lock to an > incoming SPDIF signal, but always use a local crystal clock source for > their DAC. These cards do not have their ADC and DAC synchronised. Do common on-board or PCI sound card lock to some incoming signal? Yes, there is a crystal oscillator and a PLL or divider to

Following a series of three patches, two of which have been sitting in my tree for a while, the third is the result of some inspection of an NV134 BIOS that seems to use the 0xaf upcode to upload training patterns. Please test! Roy Ps. Sorry they come from yet another e-mail address. My previous provider, eclipso, actively blocks users of git send-email. Inquiries fall on deaf ears, hence I

Following a series of patches that implement memory reclocking for NVA3/5/8 with DDR2, DDR3 and GDDR3 on board. I tested these patches on 6 different graphics cards, but I expect reclocking now to work on many more. Testers can pick up these patches and test it by enabling pstate (nouveau.pstate=1). They should then be able to change clocks by writing to /sys/class/drm/card0/device/pstate. Correct

This patch series is the final (?) step towards the initial support of GK20A, allowing it to be probed and used (currently at a very slow speed, and for offscreen rendering only) on the Jetson TK1 and Venice 2 boards. The main piece if the first patch which adds platform devices probing support to Nouveau. There are probably lots of things that need to be discussed about it, e.g.: * The way the