similar to: Will Digium Wildard work with PCI-Xor PCI Express

Hi All, I'm looking for a way to filter the AstDB cidname family to show only those entries with a specified area code in the Asterisk CLI. If this were a SQL database it would be something like: SELECT number, name FROM cidname WHERE number LIKE '1234%' I've tried "database show cidname 1234*" and substituted "%", "$", "-" for the wildcard

Just noticed this today: Digium TE220B Dual Span T1/E1 PCI Express Card with Octasic DSP-based Echo Cancellation Module<http://www.voipsupply.com/product_info.php?products_id=3352> It's about time Digium got on the ball and made PCI-e cards. What are people's experiences with this card? Anyone know if there are plans for a PCI-e analog card for FXO use? -------------- next part

Hi I'm buying a new box and it brings the new PCI-e standard and not the old PCI slots. I would like to know if the Digium Wildcard TDM400P and <http://www.digium.com/index.php?menu=wildcard_tdm400p2>Wildcard TE405P will work with this PCI Express. <http://www.digium.com/index.php?menu=wildcard_te405p> Has anybody worked with PCI-e yet? As far as i understand, the Wildcard

Hi to All, I dont know much about PCI express slots in newer Servers, my doubt is if the Digium and Sangoma PCI express cards, are compatible with the x8 PCI express slots that come in the HP Proliant ML150 G5 server. Thanks in advance. Ricardo -------------- next part -------------- An HTML attachment was scrubbed... URL:

After installing the timing source , what do I have to do to get meetme application registered? Do I have to recompile asterisk again ? I don't see the compiled meetme.so module in the directory. Regards, Sam -----Original Message----- From: asterisk-users-bounces@lists.digium.com [mailto:asterisk-users-bounces@lists.digium.com] On Behalf Of Kevin Bockman Sent: Friday, February 10, 2006

Good eye! Its getting late maybe I should just stop now Thank again! -----Original Message----- From: asterisk-users-bounces@lists.digium.com [mailto:asterisk-users-bounces@lists.digium.com] On Behalf Of Kevin Bockman Sent: Monday, March 13, 2006 8:55 PM To: Asterisk Users Mailing List - Non-Commercial Discussion Subject: Spam? Re: [Asterisk-Users] Unknown signalling method

Hello, I have figured out that my audio problem was just how I was converting the sound files. I am trying to convert the Asterisk gsm files to ULAW. I just did a: sox file.gsm file.ul, open it in Audacity. I used: Project, Import Raw, U-law, No endian, 1 channel, start offest 1 byte, sample rate 8000hz. The file sounds fine in Audacity. Now, if I do a record on Asterisk, using pcm, au, or

Hi all, I've setup a PBX in production environment last week but we have immediatly find out drop conversations and lot of errors (in asterisk logs) like: Apr 10 17:30:48 NOTICE[25154] chan_zap.c: PRI got event: HDLC Bad FCS (8) on Primary D-channel of span 2 My configuration is: Motherboard: SuperMicro P8SCT (Intel E7221 chipset) Hypertrading and APIC enabled CPU: P4 3GHz Digium TE205P

Hi, I would like to xor (bitwise) two matrices filled with binary values (0,1). The result of such XOR is expected to be 0,1. But apparently neither of xor nor bitXor is working in this case. I got ": binary operation on non-conformable arrays" error message when I used xor (M1,M2) . The problem with bitXor(M1,M2) is that it just truncates the result into a vector rather than a

Hi folks, I couldn't find a specific XOR (OR and AND) optimization on llvm, and therefore I am about to implement it. But first I would like to check with you guys that it really does not exist. For a simple loop like this: nbits = 128; bit_addr = 0; while(nbits--) { bindex=bit_addr>>5; /* Index is number /32 */ bitnumb=bit_addr % 32; /* Bit number in longword */

2011/7/26 Daniel Nicácio <dnicacios at gmail.com>: > > I also would like to see why the "XOR  A,  -1" is not turned into a NOT, any > Probably because NOT (like NEG) doesn't exist :) <http://llvm.org/docs/LangRef.html#instref> I assume the decision was made that it wasn't worth adding the extra unary instructions when they can easily be handled in codegen

SimplifyDemandedUseBits in part because of the following comment: // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. will transform %neg = xor i32 %V, -1 %and = and i32 %not, 4096 into %and = and i32 %V, 4096 %xor = xor i32 %and, 4096 which would generate worse code for platforms that have a negate instruction vs. encoding the immediate in the xor. What should happen to

Hi, On Tue, Jul 26, 2011 at 11:32 AM, Matt Johnson <johnso87 at crhc.illinois.edu>wrote: > Hi Daniel, > > > Hi folks, > > > > I couldn't find a specific XOR (OR and AND) optimization on llvm, and > > therefore I am about to implement it. > > But first I would like to check with you guys that it really does not > exist. > > > > For a

"The fact that the loop is unrolled explains why the XORs, SHLs, and ORs are not folded into 1." I dont see why the unrolling explains it. "I think he is trying to say this expression generated by unrolling by a factor of 4 can indeed be folded into a single XOR, SHL and OR. " Precisely. The code generated by unrolling can be folded into a single XOR and SHL. And even if it

Hey guys, I still think there is no optimization doing what I want. When the loop is unrolled 32 times, llvm is able to identify that the loop is working on a whole word, it finds some constants and propagate them, resulting in the folded XOR instruction. However, when the loop operates on some bits of the word, llvm is still not able to fold those XOR, even when the operated bits does not

The quilt patch titled Subject: crypto: arm/xor - add missing MODULE_DESCRIPTION() macro has been removed from the -mm tree. Its filename was crypto-arm-xor-add-missing-module_description-macro.patch This patch was dropped because it was merged into the mm-nonmm-stable branch of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm

Hi, At line 2292, lib/VMCore/ConstantFold.cpp (llvm2.7 release) Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode, Constant *C1, Constant *C2) { ... // Handle UndefValue up front. if (isa<UndefValue>(C1) || isa<UndefValue>(C2)) { switch (Opcode) { case Instruction::Xor: if (isa<UndefValue>(C1)

Hi- > I haven't seen a machine in which OR is faster than ADD nor more energy-efficient. They're all done by the same ALU circuitry which delays the pipeline by its worstcase path timing. So, for modern processor hardware purposes, OR is exactly equal ADD. Transforming ADD to OR isn't strenght reduction at all. Maybe this is benefical only if you have a backend generating circuitry

On Jul 6, 2010, at 3:37 PM, Jianzhou Zhao wrote: > Which semantics is better? I guess both are fine because if we assume > these two def's are same, then it is 0 as > 'ConstantFoldBinaryInstruction', while if we assume they are different > then it is equal to undef. But the second case seems to include the > first one. If we let undef xor undef to be undef, later we can

Hi all, How to XOR the return address on the stack with a canary word both are 32 bits? Is there a method to implement it? Thank you. Ying -- The University of Edinburgh is a charitable body, registered in Scotland, with registration number SC005336.