similar to: Current status on _outgoing_ Swedish/Dutch DTMF CLIP for TDM400 FXS interfaces?

Thanks you. I'm new to LLVM backend, so the help is much appreciated. On Sat, Oct 24, 2015 at 2:12 AM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > > On Oct 23, 2015, at 3:36 AM, 李弘宇 via llvm-dev <llvm-dev at lists.llvm.org> > wrote: > > > The first line has the following error message: > > > > sop1-playground.s:1:15: error: invalid immediate:

On 10/10/11 19:19, Jakob Stoklund Olesen wrote: > On Oct 10, 2011, at 10:26 AM, Richard Osborne wrote: >> I'm investigating a bug associated with debug information that manifests >> itself in the XCore backend (PR11105). I'd like to understand what the >> expected behavior of eliminateFrameIndex() is when it is called on a >> dbg_value machine instruction. >

On Oct 10, 2011, at 10:26 AM, Richard Osborne wrote: > I'm investigating a bug associated with debug information that manifests > itself in the XCore backend (PR11105). I'd like to understand what the > expected behavior of eliminateFrameIndex() is when it is called on a > dbg_value machine instruction. That is up to the target. The TII::emitFrameIndexDebugValue() hook is

I'm investigating a bug associated with debug information that manifests itself in the XCore backend (PR11105). I'd like to understand what the expected behavior of eliminateFrameIndex() is when it is called on a dbg_value machine instruction. Currently the XCore target replaces the frame index with the frame register and sets the next operand to the byte offset from the frame

Hello, I have been playing around with Remus on Xen 4.0.1, attempting to fail-over for an HVM domU. I''ve run into some problems that I think could be related to tapdisk2 and its interaction with how one sets up Remus disk replication in the domU config file. A few things I''ve noticed: -The tap:remus:backupHostIP:port|aio:imagePath notation does not work for me, although this

I'm working on some enhancements to rematerialization that I hope to contribute. It's mostly working but I am running into one problem. It boils down to having spilled a register used by the remat candidate. I thought this is what getReMatImplicitUse is supposed to handle but it looks inconsistent to me. The comment says this: /// getReMatImplicitUse - If the remat definition MI has

I have registers that can hold either integer or floating point values. There are instructions for integer operands, floating operands, and also a "mixed" type operand, ie an operand that is the result of either an integer or floating point operation. I see that the RegisterClass has a list of ValueTypes, and I conclude that I can define a register class to use for the mixed operands

Dear Developers, I compile a OpenCL kernel, FFT, in AMDAPP SDK v2.5 using clang 3.8 + libclc and assembling the code with lld (The LLVM linker). The assembly code contains the following assembly codes (and lots of other similar format assembly) that fails to be parsed by AMDGPUAsmParser. It seems to me that both are valid instructions after looking at the SI instruction spec. s_mov_b32 s0,

Roman Levenstein wrote: > Hi again, > > Now, after I fixed the graph coloring regalloc bug that was triggered > by the ARM target, I continue testing and found another bug, this time > on the XCore target. First I thought that it is again specific to my > register allocator, but it seems to be trigerred also by LLVM's > linearscan register allocator. > > I don't

On Jan 13, 2009, at 11:20 AM, Richard Osborne <richard at xmos.com> wrote: > Roman Levenstein wrote: >> Hi again, >> >> Now, after I fixed the graph coloring regalloc bug that was triggered >> by the ARM target, I continue testing and found another bug, this >> time >> on the XCore target. First I thought that it is again specific to my >>

Hi again, Now, after I fixed the graph coloring regalloc bug that was triggered by the ARM target, I continue testing and found another bug, this time on the XCore target. First I thought that it is again specific to my register allocator, but it seems to be trigerred also by LLVM's linearscan register allocator. I don't know if the XCore target is stable enough in LLVM, or may be I

Hi All, In the target I am working, we comes cross a situation that the loop strength reduction could deliver a better result but currently not, because 1. the algorithm narrows search space by winner registers without considering the target preferred format. (NarrowSearchSpaceByPickingWinnerRegs) 2. Cost comparison solely favors the number register without considering other

Hi Andy, Actually, if we just add hooks that preserves the existing behavior, It is not difficult. For example, For case one, we can define one function like virtual const SCEV* getTargetPreferredWinnerReg(const SCEV*& ScaledReg, SmallVector<const SCEV *, 4>& BaseRegs, GlobalValue*& BaseGV) const; In NarrowSearchSpaceByPickingWinnerRegs, we can

On Mar 13, 2013, at 4:37 PM, Yin Ma <yinma at codeaurora.org> wrote: > Hi All, > > In the target I am working, we comes cross a situation that the loop strength reduction > could deliver a better result but currently not, because > 1. the algorithm narrows search space by winner registers without considering > the target preferred format.

----- Original Message ----- > From: "Yin Ma" <yinma at codeaurora.org> > To: "Andrew Trick" <atrick at apple.com> > Cc: llvmdev at cs.uiuc.edu > Sent: Thursday, March 14, 2013 4:21:50 PM > Subject: Re: [LLVMdev] Suggestion About Adding Target Dependent Decision in LSR Please > > > > > > Hi Andy, > > > > Actually,

Hi Justin, After catching up with LLVM trunk, I've encountered a new backend issue around i1. Is i1 support still incomplete? Bug report: http://llvm.org/bugs/show_bug.cgi?id=17519 Thanks, - D. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131009/4ca2cbdd/attachment.html>

I just want to know ,how can I developing a LLVM Pass on Windows' visual studio? I can develop a Pass on linux,but I can't do it on windows. 2013/3/15 <llvmdev-request at cs.uiuc.edu> > Send LLVMdev mailing list submissions to > llvmdev at cs.uiuc.edu > > To subscribe or unsubscribe via the World Wide Web, visit >

Hi, After some testing I've found out that my client's hardware recognizes DTMF only if digits are sent 50ms apart with 50ms of tone duration. This was tested using a test device which generates DTMF. Now asterisk doesn't do it by default because digits going out from Asterisk are not being recognized. Using command sendDTMF, I can control inter-digit duration, and using

Hi, We are running 1.4.22 and have been experiencing problems with certain IVRs and DTMF Tone duration. We would like to be able to increase DTMF Tone duration by 50 to 100ms over what the user is pressing on his phone. We have a PRI test circuit and an analyer in between to measure tone duration. We have tried setting chan_dahdi.conf parameter 'toneduration', but that does not do

My outgoing FXO calls are answered but have no audio in either direction if I have callprogress=no in chan_dahdi.conf. If I change to callprogress=yes then the audio returns. My chan_dahdi.conf file is listed below. Can anyone point-out why callprogress=no isn't working? #cat /tmp/a [trunkgroups] [channels] language=en context=incoming toneduration=40 ;usedistinctiveringdetection=yes