similar to: Re: [Asterisk-Dev] The killer app for Asterisk in corporate deployment

We're a dealer in Europe selling commercial phone & building management systems, some residential too. All the new office buildings have an EIB bus to manage the lights, clima, security access, etc. The big companies also have Crestron or AMX automation and media servers for the boardroom. Asterisk is an awesome phone solution, but if we could offer a solution that tied it all together

Hi Philip, Your idea make sense to me in my first thought. Thank you for the idea. I will take more time to think it over to see it can help to reduce the complexity of tile register allocation. Yuanke From: Philip Reames <listmail at philipreames.com> Sent: Saturday, August 15, 2020 11:29 AM To: Luo, Yuanke <yuanke.luo at intel.com>; llvm-dev at lists.llvm.org; florian_hahn at

Hi, We are having major problems with a remote site that links to the head office via a VPN tunnel. The phones will register fine and work for a few minutes to hours but then will drop their connection and will no register to asterisk even with a restart of the phone. We have 2 other remote sites that work exactly same and they are not having any issues so i believe it has to be be something

From: Hal Finkel <hfinkel at anl.gov> Sent: Friday, August 14, 2020 11:27 PM To: Luo, Yuanke <yuanke.luo at intel.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Kaylor, Andrew <andrew.kaylor at intel.com>; Topper, Craig <craig.topper at intel.com>; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: Re: [llvm-dev] Intel AMX programming model discussion. On

Hi Yuanke, As I said on the review, I think at least Craig should have a look and approve before landing, as this is a major change in the x86 back-end. cheers, --renato On Thu, 19 Nov 2020 at 02:29, Luo, Yuanke via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hi, > > > > Several months ago, we have some discussion for Intel AMX programming > model in llvm-dev. H.J.

Hi, Several months ago, we have some discussion for Intel AMX programming model in llvm-dev. H.J. post the AMX ABI at [1], and I sent the design for the programming model at [2]. Thank Hal, Philip for the time to review the design and provide good ideas to improve the design. After that I implemented the patch [4] and it is reviewed in LLVM community. The patch covers 6 components. 1. The c

The AMX registers are complicated. The single configuration register (which is mostly used implicitly, similar to MXCSR for floating point) controls the shape of all the tile registers, and if you change the tile configuration every single tile register is cleared. In practice, if we have to change the the configuration while any of the tile registers are live, performance is going to be terrible.

[Yuanke] AMX register is special. It needs to be configured before use and the config instruction is expensive. To avoid unnecessary tile configure, we collect the tile shape information as much as possible and combine them into one ldtilecfg instruction. The ldtilecfg instruction should dominate any AMX instruction that access tile register. On the other side, the ldtilecfg should post-dominated

Hi Hal, There is 3 aspect to be solved. 1. The HW support max shape 16x16, so there are many register classes from 1x1 to 16x16. We need 256 register classes. 2. We want to support variable shape, so compiler don't know what register class to fit tile shape as it is only known in runtime. 3. The tile configure is to configure physical tile register, so we need to allocate

On 8/20/20 2:47 PM, Topper, Craig wrote: > > I think I’m still missing something here. The configuration is per > tile. The multiply instructions take a MxK tile and multiply it by a > KxN tile and accumulate into an MxN tile. So the configuration needs > to know how many of each size of tile it needs to avoid a spill. > Wouldn’t the register allocator then need to know which

Hi Hal, The proposal is attractive to me, but there is something I still can't figure out. Let's take below MIR as an example. We assume we have 256 register classes (vtile1x1, vtile1x2, ..., tile16x16). 1. After instruction selection, the pseudo AMX instruction is generated. The name of pseudo instructions have 'P' prefix. Now all the AMX pseudo instruction take vtile as

> When the tile shape is unknown at compile time, how do you plan to do the register allocation of the tiles? My question is: do you do the allocation for this case in the same way as you would if you knew the size was 16x16 (i.e., conservatively assume the largest size)? I think what will happen is that the registers are allocated based on a number of runtime values that are assumed to be

There is no problem to have 256 register classes. Just a lot of register classes to me. We don't assume the shape of each physical register be 16x16, it is defined by user. For variable shape, I mean the shape is known in runtime and in compile time the shape is unknown. Take below code as an example, the %row and %col are variable instead of constant. Compiler recognizes llvm.x86.tileloadd64

Hi, Intel Advanced Matrix Extensions (Intel AMX) is a new programming paradigm consisting of two components: a set of 2-dimensional registers (tiles) representing sub-arrays from a larger 2-dimensional memory image, and accelerators able to operate on tiles. Capability of Intel AMX implementation is enumerated by palettes. Two palettes are supported: palette 0 represents the initialized state and

R friends, I am using R 2.1.0 in a Win XP . I have a problem working with lists, probably I do not understand how to use them. Lets suppose that a set of patients visit a clinic once a year for 4 years on each visit a test, say 'eib' is performed with results 0 or 1 The patients do not all visit the clinic the 4 times but they missed a lot of visits. The test is considered positive if it

The width and height can be runtime values that we would just copy into 64 byte configuration block we pass to ldtilecfg. So the code doesn't need to be multiversioned. The user code would also use those values to update pointers in the loops they write using the tiles. If we can't determine that two tiles were defined with the same width and height we need to assume the shape is different

Hi Benno, --- Benno Senoner <sbenno@gardena.net> wrote: > Hi, sorry for writing you directly, It's no trouble, though you may get more or better advice posting to one of the mailing lists or on irc (#winehq). I'm cc'ing wine-users in case someone else has experience in this area, hope you don't mind. > assume I use LabView on Windows to make a standalone .exe >

Fix typo From: Luo, Yuanke Sent: Friday, September 4, 2020 9:47 PM To: 'Hal Finkel' <hfinkel at anl.gov>; Topper, Craig <craig.topper at intel.com>; Kaylor, Andrew <andrew.kaylor at intel.com>; Philip Reames <listmail at philipreames.com>; llvm-dev at lists.llvm.org; florian_hahn at apple.com; Lu, Hongjiu <hongjiu.lu at intel.com> Subject: RE: [llvm-dev]

Hi, Yuanke, Thanks for writing this up. Let me back up a bit because the scheme I proposed last week doesn't work without further modification: within a particular "configuration region" (i.e., the code in between the LDTILECFG and the TILERELEASE (or next LDTILECFG)), each tile register can only be used with one shape, and in addition, no register can have its shape changed

Hi All, Thanks for all of the help I've been given in the past and info I've picked up from this list over the years. I have an "official" Asterisk appliance (the AA50) running my PBX at home (we previously also had an AA50 in a satellite office-that one was recently retired and replaced with Asterisk running on commodity server hardware). Anyway - the AA50