similar to: IAX2 --> IAX2 confusion, it doesn't work...

Hi, Lars Thanks for your suggestion, will give it a try later to see how it performs. But, yesterday, I did a below test: A ConnectTo B and C, B ConnectTo D, C ConnectTo D; All nodes turned "IndirectData" on in its host configuration, so the tunnel only follow metacomnection instead of direct connect. D announced default route by having the Subnet = 0.0.0.0/0 statement in its host

Hi, Tinc expert If there’re multiple tinc nodes announce default route in their host configuration of Subnet = 0.0.0.0/0, how for the remaining nodes to select which is the best route to get out? All of them participant in the same tinc net. I did some test, like A as the branch, B,C,D as the nodes to announce default route; when all up , A select B, but if B down, A will go C, C down, A will

Sure, let me reply all here for my finding. @Lars @Guus A’s tinc.conf: Name = bright AddressFamily = ipv4 ConnectTo = aly_hk A’s tinc-up: #!/bin/sh ifconfig $INTERFACE 10.0.0.110 netmask 255.255.255.0 A’s host config: Subnet = 10.0.0.110/32 (VPN address) Subnet = 192.168.31.0/24 (LAN address) IndirectData = yes (enabled for every tinc nodes) The node aly_hk (vpn address 10.0.0.3) connects with

Hi Xi, How did you compile it with clang? I ran into problems: clang -emit-llvm -DPACKAGE_NAME=\"newlib\" -DPACKAGE_TARNAME=\"newlib\" -DPACKAGE_VERSION=\"1.19.0\" -DPACKAGE_STRING=\"newlib\ 1.19.0\" -DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -I. -DMISSING_SYSCALL_NAMES -fno-builtin -DMISSING_SYSCALL_NAMES -fno-builtin -O2 -c -o

I would recommend Newlib. It's easy to configure and compile using Clang. http://sourceware.org/newlib/ - xi On Jun 23, 2011, at 2:07 AM, Gregory Malecha wrote: > Hello, > > I'm wondering if anyone had any success (even a small amount) compiling any variant of libc to llvm bitcode? > > -- > gregory malecha > _______________________________________________ >

I am currently trying to compile a pretty simple program to work on an experimental board. It contains an (FPGA-version of) an ARMv4 processor. So basically, I try this (on my Ubuntu 18.04.1 LTS): clang -v --target=arm-none-eabi -c barehello.c -o barehelloCLANG.o clang -v --target=arm-none-eabi -c io.c -o io.o clang -v --target=arm-none-eabi barehelloCLANG.o io.o -o helloCLANGstatic -static

Hello, I'm wondering if anyone had any success (even a small amount) compiling any variant of libc to llvm bitcode? -- gregory malecha -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110622/b5fad437/attachment.html>

Hello, on the problems cross-building compiler-rt: Tried to follow https://llvm.org/docs/HowToCrossCompileBuiltinsOnArm.html which lead to this cmake: cmake -G "Ninja" ../llvm/projects/compiler-rt/ -DCOMPILER_RT_BUILD_BUILTINS=ON -DCOMPILER_RT_BUILD_SANITIZERS=OFF -DCOMPILER_RT_BUILD_XRAY=OFF -DCOMPILER_RT_BUILD_LIBFUZZER=OFF -DCOMPILER_RT_BUILD_PROFILE=OFF

Hi, I'm trying to enable the hexagon LLVM assembly parser. It seem like there is a lot of work that has been done to make this parsing straightforward. But.. Hexagon assembly does not follow the "Mnemonic Rx Rx ." format that is expected by the assembly parsing infrastructure, represented by: StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken(); This

Hello all, I am at the adding Instruction Set stage of adding new target support into LLVM. There is a single instruction op mnemonic with multiple operand forms. For example: Add R1, R2 & Add @R1, R2. I found that there is similar case in x86 instruction set, such like ADD reg, reg & ADD mem, reg. However, the solution of x86 is adding suffix of instruction and translating instruction op

Hello again! Tried out the small Hello World Setup, worked as intended: root at christian-forschung-virtual-machine:/home/progs# clang -v --target=arm-linux-gnueabihf hello.c -o hello -fuse-ld=lld clang version 8.0.0 (https://git.llvm.org/git/clang.git/ a152c7a4b7ba8f4cb9532ead9a38a7121db43d50) (https://git.llvm.org/git/llvm.git/ 1959ce6f3e01241919968ac1911fd45660239d23) Target:

Hello again Christian, I've posted https://reviews.llvm.org/D55709 to see if we can get the documentation on how to cross-compile compiler-rt improved. I'll be out of office until next year so I may be a bit slow to respond to any follow ups. Peter On Thu, 13 Dec 2018 at 17:10, Peter Smith <peter.smith at linaro.org> wrote: > > Hello Christian, > > I've just

On Oct 17, 2012, at 3:29 PM, David Young <davidy at codeaurora.org> wrote: > Hi, > I’m trying to enable the hexagon LLVM assembly parser. It seem like there is a lot of work that has been done to make this parsing straightforward. > > But…. > Hexagon assembly does not follow the “Mnemonic Rx Rx …” format that is expected by the assembly parsing infrastructure,

Hello Peter and Lists, thanks a lot, that way it worked out! The final cmake was cmake -G "Ninja" ../llvm/projects/compiler-rt/ -DCOMPILER_RT_BUILD_BUILTINS=ON -DCOMPILER_RT_BUILD_SANITIZERS=OFF -DCOMPILER_RT_BUILD_XRAY=OFF -DCOMPILER_RT_BUILD_LIBFUZZER=OFF -DCOMPILER_RT_BUILD_PROFILE=OFF -DCMAKE_C_COMPILER=/usr/local/myclang/bin/clang -DCMAKE_AR=/usr/local/myclang/bin/llvm-ar

I'm trying to implement the standalone assembler for mips and I have encountered a problem in instruction operands matcher. In mips instruction set there are math instructions with two format flags in the mnemonic, one for source and one for destination register. For example ceil.w.s means both source and destination are F32 registers while ceil.l.d means both source and destination are F64

Hi, I'd like to modify MachineBasicBlock contents within a MachineFunctionPass on the basis of how many CPU cycles the assembly instructions corresponding to the MBB take. I'm using the AVR backend and the number of CPU cycles every AVR assembly operation takes is openly available. Is there any straightforward way of getting the opcode mnemonics corresponding to a MachineInstr? I've

Thanks for the quick answer Bruce. So far as I can tell (from a quick read), this is really for integrated assemblers/disassemblers - but we use an external assembler. When invoking clang we would provide ‘-mcpu=chip_v1’ or ‘-mcpu=chip_v2’, and the mnemonic ‘LD32’ is only valid when compiling for ‘chip_v1’, while ‘LD.32’ is only valid when compiling for ‘chip_v2’. But I will study the

Hello Christian, I've put some comments inline, On Sun, 3 Feb 2019 at 13:11, Christian Richter <christian.richter at hsu-hh.de> wrote: > > Hello again, > > so after I successfully build the compiler-rt for armv6 I tried to > actually use it in compiling a small helloworld for a baremetal arm > (consisting of barehelloCLANG.c and a small io.h + io.c) , but the >

Hello all, I would like to assign some bits in the instructions, based on the order of mnemonics that appear in a special order. I can do it in TableGen itself, but it will not be well maintainable based on the things I want to accomplish. Therefor, I would like to do it in the c++ file which is waaay easier (at least in the concept!!). Imagine I have this in my base class in TableGen:

Hi, I have two * box. One is box1 and the other is box2. And I have two iax clients A and B. A is registed with box1 and B is registed with box2. If I make a call from A to B using the following method: IAX/[<user>[:<secret>]@]<peer>[:<portno>][/<exten>[@<context>][/<options>]] The CalledID that B got is <user> but not A's CallerID. I