similar to: 3Com Cards

Displaying 20 results from an estimated 1000 matches similar to: "3Com Cards"

2004 Jan 26
1
3com 3c905b - pxe boot failure
Hi, I'm trying to boot a clean machine(hostname=dgrid-5.srce.hr) with 3com 3c905b NIC (ver4.30 MBA) with pxe. Server: hostname: dgrid-1.srce.hr pxelinux.0: syslinux-2.08 tftp: tftp-hpa-0.36 dhcp server: dhcp-2.0pl5-8 Client: boot option: DHCP Client machine successfully gets pxelinux.0 and then everything stops(see listing below). I've tried with xinetd-2.3 and
2014 Jan 15
2
[LLVMdev] test suite 'owner'
thank you. I'll submit the patch without #ifdef in this case. Robert ________________________________ From: dblaikie at gmail.com [dblaikie at gmail.com] Sent: 14 January 2014 17:03 To: Robert Lytton; echristo at gmail.com; llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] test suite 'owner' On Mon Jan 13 2014 at 12:25:14 PM, Robert Lytton <robert at xmos.com<mailto:robert at
2002 Mar 08
0
PXELINUX: suggestion for improvement
Hi, We're planning to deploy PXELINUX as a primary kernel loader in cluster environment. Problem is that we plan to have IP numbers assigned dynamically while there is no guarantee that all machines has same CPU architecture. This makes IP-based config search algorithm inappropriate for our purposes because we [naturally] expect loaded kernel to match hardware. For this reason I've
2014 Jan 13
2
[LLVMdev] test suite 'owner'
... and so (I infer from that) it should not be patched let alone need any changes. Assuming my inference is correct, any patching should only affect the XCore target and only if there is a good reason why the XCore requires the change. So, is #ifdef around all/most changes the correct way to submit a patch? Robert ________________________________ From: Eric Christopher [echristo at gmail.com]
2006 Feb 07
2
pxelinux don't uncompress kernel and initrd
Hallo, for last Friday, i have a strangely probleme with one of oure clients. I can power on , the bootprom make the connection to the dhcpserver, the client load the pxelinux , it load the kernel and the initrd.img, say ready and this was it. It dont uncompress the initrd and the kernel . I can wait a long ime and the only that I can do is ctrl-alt-del. It give no error code. I have more
2013 Aug 22
0
[LLVMdev] PrescheduleNodesWithMultipleUses() causing failure in PickNodeToScheduleBottomUp() ???
sorry, Just noticed that the diagrams have 'Destroy' & 'SetUp' the wrong way around! Robert ________________________________ From: llvmdev-bounces at cs.uiuc.edu [llvmdev-bounces at cs.uiuc.edu] on behalf of Robert Lytton [robert at xmos.com] Sent: 21 August 2013 18:34 To: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] PrescheduleNodesWithMultipleUses() causing failure in
2019 May 14
2
weakforced and GeoIP lookups
Hi Tobi, it should just work, but depends on the OS version. ./configure ?help tells you all the configure options, including: --with-maxminddb-includedir path to maxminddb include directory [default=auto] --with-maxminddb-libdir path to maxminddb library directory [default=auto] Neil > On 14 May 2019, at 17:44, Tobi via dovecot <dovecot at dovecot.org>
2019 May 14
0
weakforced and GeoIP lookups
Hi Neil according to yum list installed I have > libmaxminddb-devel.x86_64 1.2.0-1.el7 @epel but I checked the saved output from my former ./configure command and found > checking for GEOIP... no but even running a new autoreconf -i and ./configure after a make clean it still shows that GEOIP is not found. Does the lib has to explicitly specified as argument
2019 May 14
2
weakforced and GeoIP lookups
Hi Tobi, This looks like you haven?t included the libmaxmind libraries before running configure. GeoIP support is only compiled in if it finds the right libs. This would be libmaxminddb-dev on Ubuntu for example. Neil >> Hi list >> >> hope it's okay to ask weakforced questions here as well, but I could not >> find a dedicated mailinglist for wforce. >>
2014 Feb 26
3
[LLVMdev] test-suite wrongly using big-endian results
On 26 February 2014 14:44, Robert Lytton <robert at xmos.com> wrote: > This is related to a patch I submitted a little while ago (still pending): > http://llvm-reviews.chandlerc.com/D2760 > > If accepted, would it make this patch (and a others) unnecessary? Hi Robert, It is, but hijacking your patch a little, why not use __ORDER_LITTLE_ENDIAN__? Why do we need to create
2014 Jan 13
4
[LLVMdev] test suite 'owner'
Hi Eric, Could you explain the intent and policy regarding the test-suite body of code. Should the test be left as much as possible as-is (even if technically incorrect)? Should changes only affect the XCore target (#ifdef) or should all targets get the changes? Taking "int32_t main" as an example. The correct return type & argc for main is 'int'. In the XCore tool chain,
2013 Jul 05
0
[LLVMdev] making a copy of a byval aggregate on the callee's frame
Hi Robert, suppose you have a "byval" argument with type T*, and the caller passes a T* called %X for it, while in the callee the argument is called %Y. The IR level semantics are: (1) a copy should be made of *%X. Whether the callee or the caller makes the copy depends on the platform ABI. (2) in the callee, %Y refers to the address of this copy. There are many ways (1) can be
2013 Aug 21
2
[LLVMdev] PrescheduleNodesWithMultipleUses() causing failure in PickNodeToScheduleBottomUp() ???
Hi, I have reasoned through and believe the problem is with the PrescheduleNodesWithMultipleUses. Take the following DAG (arrow to predecessor): Destroy Destroy ^ ^ | | | | SetUp----->PredSU <-----SU ^ ^ ^ | | | | | | ----------- |
2013 Jul 05
0
[LLVMdev] making a copy of a byval aggregate on the callee's frame
Hi Tim, Correction to my last email. What I should have said is that the new pointer is used by the callee rather than the original byVal pointer arg. (the byVal pointer arg remains but is not used by the callee). viz: define void @f1(%struct.tag* byval) { entry: %st = alloca %struct.tag, align 4 %1 = bitcast %struct.tag* %st to i8* %2 = bitcast %struct.tag* %0 to i8* call void
2010 Dec 14
1
Setting Battery Runtime Low
Dear All, We have an Eaton 9395 UPS, with a ConnectUPS Web/SNMP card. I've successfully configured NUT to talk to the SNMP card, however it reports a battery.runtime.low of 1 , not much use, how do I change this value, is it defined by the UPS itself, the SNMP card, or NUT ? Output of upsc below. Cheers Stuart rcs-manage-1:~ # !upsc upsc phys-eaton ambient.temperature: 27.0
2013 Aug 22
0
[LLVMdev] PrescheduleNodesWithMultipleUses() causing failure in PickNodeToScheduleBottomUp() ???
On Thu, Aug 22, 2013 at 4:15 AM, Robert Lytton <robert at xmos.com> wrote: > > > Outstanding issues > ============ > > 1. Is it too aggressive in searching predecessors and successors? > Should the algorithm give up and assume the worst if the depth of > search reaches a predefined limit? > > 2. Should the initial search for 'SetUp1' and
2006 Nov 01
4
My Phone Review- Large Scale Corp Deployment.
I have had the opportunity to test many IP phones in the last 6 months and I thought you might enjoy a quick review of what I have found. Grandstream Budgtone 200 - Poor Quality for business use- Looks good, and the handset feels nice, buttons have a decent feel, but the disply is difficult to read when you are not directly over head of the phone, plus the sound quality of the handset, and
2020 Mar 11
2
XCore target
Hello all. At XMOS we are working towards updating the upstream XCore backend for newer versions of the chip. XCore is the XMOS processor. The XCore backend was written by Richard Osborne at XMOS. Richard has moved on. The current code owner in CODE_OWNERS.TXT, Robert Lytton, has also moved on. For some years XMOS has developed the compiler in-house, for new versions of the chip, but not
2013 Sep 10
0
[LLVMdev] removing unnecessary ZEXT
Hi, A bit more information. I believe my problem lies with the fact that the load is left as 'anyext from i8'. On the XCore target we know this will become an 8bit zext load - as there is no 8bit sign extended load! If BB#1 were to force the load to a "zext from i8" would this information be available in BB#2? BB#1: 0x268c1b0: i32 = Register %vreg1 [ID=3] 0x2689d80:
2013 Sep 11
2
[LLVMdev] removing unnecessary ZEXT
On Sep 10, 2013, at 8:59 AM, Robert Lytton <robert at xmos.com> wrote: > Hi, > > A bit more information. > I believe my problem lies with the fact that the load is left as 'anyext from i8'. > On the XCore target we know this will become an 8bit zext load - as there is no 8bit sign extended load! > If BB#1 were to force the load to a "zext from i8" would