similar to: Bug report

Hi Krzysztof, Sure, please see below. DAG.dump.() before and after, annotated with what I believe the DAG means. I've spent some time debugging the method but it's proving difficult to determine where the logic is misfiring. Disabling the entire combine causes a lot of failing x86-64 tests - I may have to learn an upstream vector ISA to make progress on this. Thank you >From your

Hi all, Our target does not have native support for 64-bit integers, so we rely on library calls for certain operations (like sdiv). We recently ran into a problem where these operations that are expanded to library calls aren't maintaining the proper ordering in relation to other chains in the DAG. The following snippet of a DAG demonstrates the problem. t0: ch = EntryToken t2:

Hello. I'm having problems at instruction selection with my back end with the following basic-block due to a vector add with immediate constant vector (obtained by vectorizing a simple C program doing vector sum map): vector.ph: ; preds = %vector.memcheck50 %.splatinsert = insertelement <8 x i64> undef, i64 %i.07.unr, i32 0

Hello, I've hit an assertion in SelectionDAG where we try to merge 2 loads that have the same operands but their MMO flags differ. One is dereferenceable and one is not. I'm not sure what the underlying issue here is: 1) MDSDNode with the same operands should have the same flags set on their respective MMO. The fact the flags differ when the opcode,types,operands and address-space are

Hello. I'm writing a back end for a RISC processor (similar to BPF) with a large SIMD unit. I tried in the last days to make llc compile to SIMD code the following LLVM program: define i32 @foo(i32* %A, i32* %B, i32* %C, i32 %N) #0 { entry: ;vector.body: ; preds = %vector.body, %vector.body.preheader.split.split %0 = getelementptr inbounds i32, i32* %A, i64 0 ; i64 %index ; Alex: I

Hi Jonas, I have another case that DBG_VALUE is not produced. I would appreciate it if you could take a quick look at the testcase below. test code: llc -mtriple=aarch64 -stop-after=livedebugvalues -o - test.ll ; Function Attrs: nounwind ssp uwtable define void @f() #0 !dbg !4 { entry: tail call void @h(i16 0) #2, !dbg !14 %call = tail call i16 (...) @g() #2, !dbg !15 tail call void

Thanks! It looks like SelectionDAG::salvageDebugInfo handles only addition with constant. Sejong From: aprantl at apple.com <aprantl at apple.com> Sent: Monday, April 30, 2018 1:53 PM To: Se Jong Oh <sejooh at microsoft.com> Cc: jdevlieghere at apple.com; Vedant Kumar <vsk at apple.com>; llvm-dev at lists.llvm.org; pidgeot18 at gmail.com Subject: Re: [llvm-dev] [SelectionDAG]

> On Apr 30, 2018, at 1:49 PM, Se Jong Oh <sejooh at microsoft.com> wrote: > > Hi Jonas, > > I have another case that DBG_VALUE is not produced. I would appreciate it if you could take a quick look at the testcase below. > > > test code: > > llc -mtriple=aarch64 -stop-after=livedebugvalues -o - test.ll > > ; Function Attrs: nounwind ssp uwtable >

Hello, Tim, Thank you for your advice. Indeed, the problem with "LLVM ERROR: Cannot select" was a false predicate that should have been true. I solved the problem by simply making the C++ function implementing the TableGen predicate used in my store instruction (very similar to the selectIntAddrMSA predicate from the Mips back end) return true instead of false. But

Dear all, I am having a data for 2 different treatments with different time points. So, I used the following code to plot the boxplot and also to do anova. T11 <- c(280, 336, 249, 277, 429) T12 <- c(400, 397, 285, 407, 313) T13 <- c(725, 373, 364, 706, 249) T21 <- c(589, 257, 466, 248, 913) T22 <- c(519, 424, 512, 298, 907) T23 <- c(529, 479, 634, 354, 1015) obs <- c(T11,

OK, I have a strange problem. It is probably something simple/stupid, but I cannot figure it out. I have a nice new PowerEdge T20 that I installed CentOS 6 (6.5) on with Virtualization (KVM). I then installed Ubuntu 14.04 in a virtual machine, with a bridged network: ------ begin ub140464.xml------------------ <domain type='kvm' id='2'>

There are two ways to express file paths with the Windows environment: > a=file.choose() > a [1] "C:\\Documents and Settings\\rbaer\\Desktop\\_VNT_Test\\coordFocused 20k F5 0ng Ki8751 t20.txt" and >b= paste(getwd(),"/",dir()[1],sep="") >b [1] "C:/Documents and Settings/rbaer/Desktop/_VNT_Test/coordFocused 20k F5 0ng Ki8751 t20.txt" I have 2

I come across a situation that I am having a hard time to understand. When I compile the following code : char *tst( char *dest, const char *src, unsigned int len ) { for (int i=0 ; i<len ; i++) { dest[i] = src[i]; } return dest; } Clang generates this for the ‘for’ body: for.body: ; preds = %for.cond %arrayidx = getelementptr inbounds i8,

Hi, R-users, I met a problem: Items:[Anna 'moi =) akku loppu joskus 4ltä. Kestää kauan nää..'\tAmer, Tuusula (0:20)\t20\t12\t16\t00\t00\t11]/Anne 'Ei jakoa,uus päivä muistio et 4n niin peruin. Hups'\t (0:16)\t0\t12\t18\t00\t00\t11/Elina 'Konsertissa. En tod. vastaa teille'\tEtu-Töölö, Helsinki (2:40)\t24\t12\t18\t00\t00\t11 I want to parsing the above data into the

Hi, I am having some issues with how some of the instructions are being legalized. So this is my intial basic block. The area of concern is the last three instructions. I will pick and choose debug output to keep this small. SelectionDAG has 36 nodes: t0: ch = EntryToken t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17

int %nlz10(uint %param.x) { %.t3 = shr uint %param.x, ubyte 1 ; <uint> [#uses=1] %.t4 = or uint %.t3, %param.x ; <uint> [#uses=2] %.t7 = shr uint %.t4, ubyte 2 ; <uint> [#uses=1] %.t8 = or uint %.t7, %.t4 ; <uint> [#uses=2] %.t11 = shr uint %.t8, ubyte 4 ; <uint> [#uses=1]

Hi, SystemZ supports @llvm.ctlz.i64() natively with a single instruction (FLOGR), and lesser bitwidth versions of the intrinsic are promoted to i64. For some reason, this leads to unfolded additions of constants as shown below: This function: define i16 @fun(i16 %arg) {   %1 = tail call i16 @llvm.ctlz.i16(i16 %arg, i1 false)   ret i16 %1 } ,gives this optimized DAG as input to instruction

I have two boxes for the purpose of testing traffic control and my knowledge thereof (which is at the inkling stage). The boxes are connected by 100Mbit ethernet cards via a switch. For egress traffic via eth0 I achieve a throughput that is close to the specified CEILing, particularly for values above 1mbit. Ingress traffic does not seem so well behaved. Above about 1mbit rates achieved are

But isn't kinda silly that we transform to xor and then we transform it back. What is the advantage in doing so? Also, since we do that method, I now have to introduce setcc patterns for i1 values, instead of being able to just use logical pattern operators like not. -Dilan On Fri, Jul 21, 2017 at 11:00 AM Dilan Manatunga <manatunga at gmail.com> wrote: > For some reason I

On 10/20/2016 9:28 AM, Cameron McInally via llvm-dev wrote: > I should have attached the generated asm to save some trouble. > Apologies for that and attaching now... > > > > On Thu, Oct 20, 2016 at 12:26 PM, Cameron McInally > <cameron.mcinally at nyu.edu> wrote: >> On Thu, Oct 20, 2016 at 12:05 PM, Mehdi Amini <mehdi.amini at apple.com> wrote: