similar to: isolinux bug?

I'm trying to implement *MUL_LOHI for my processor. My processor has mulxss (e.g.) that gives the 32 high bits of a 64 bit multiply. I tried this in ios2ISelDAGToDAG.cpp: /// Mul/Div with two results case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { SDValue Op1 = Node->getOperand(0); SDValue Op2 = Node->getOperand(1); AddToISelQueue(Op1);

Hi, Let's say I have 2 domains: - Virtual Mailbox Domain: example.local (internal domain) - Virtual Alias Domain: example.com (public domain) Every mail sent to @example.com is really sent to @example.local. I have a virtual alias that forward mails sent to support-abc at example.com is sent finally to: op1 at example.local Now, I'd want to every mail was sent to support-abc at

Peter Zotov писал 09.01.2013 19:59: > Hello. > > I've managed to create a bitcode file (attached; also available at > [1]) which produces > a series of identical errors when verified: > > | Global variable initializer type does not match global variable > type! > | %i.NilClass* @nil > > When ran through llvm-dis and recompiled, through, it verifies >

hi, i'm new in R and i need some help. Please, ¿do you know a function how can process cross tables for many variables and show the result in one table who look like this?: +----------------------------------------------------+ |------------------ | X variable | |----------------- | Xop1 | Xop2 | Xop3|.....| +----------------------------------------------------+ |Yvar1 |

The langref says for the 'add' instruction: Syntax: <result> = add <ty> <op1>, <op2> ; yields {ty}:result <result> = nuw add <ty> <op1>, <op2> ; yields {ty}:result <result> = nsw add <ty> <op1>, <op2> ; yields {ty}:result <result> = nuw nsw add <ty> <op1>, <op2> ;

On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > Bill Wendling wrote: >> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >> >>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>> >>>> Our architecture has 1-bit boolean predicate registers. >>>> >>>> I've defined comparison >>>> >>>> def

On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > Our architecture has 1-bit boolean predicate registers. > > I've defined comparison > > > def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; > > > > > But then I end up having the following bug: > >

Our architecture has 1-bit boolean predicate registers. I've defined comparison def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; But then I end up having the following bug: Code %0 = zext i8 %data to i32 %1 = zext i16 %crc to i32 %2 = xor i32 %1, %0 %3 = and i32 %2, 1 %4 =

Bill Wendling wrote: > On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > >> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >> >>> Our architecture has 1-bit boolean predicate registers. >>> >>> I've defined comparison >>> >>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set

Introduction: We would like to add new keyword to 'sdiv'\'udiv' instructions i.e. 'no-overflow'. This is the updated solution devised in the discussion: http://lists.llvm.org/pipermail/llvm-dev/2017-October/118257.html The proposed keywords: "nof" stands for 'no-overflow' Syntax: <result> = sdiv nof <ty> <op1>,

On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > >> Our architecture has 1-bit boolean predicate registers. >> >> I've defined comparison >> >> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;

El 30 nov. 2017 4:02 a.m., "Steffen Kaiser" <skdovecot at inf.h-brs.de> escribi?: -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On Wed, 29 Nov 2017, Sergio Belkin wrote: Now, I'd want to every mail was sent to support-abc at example.com it triggers > an autoreply vacation style. > > So, I've wrote and compiled a sieve filter, something like that and put in >

Hi, Nick, thanks for the reply. I still have a problem: I only need to "clone" an Instruction, changing its type. That is, I would like to keep all characteristics of the old Instruction and create a new one only with a different type. I am trying create a new Instruction thus: %3 = add nsw i32 %1, %2 ; <i16> [#uses=2] //Old Instruction Value* Op0 = I->getOperand(0); Value*

Hello, I'm trying to fminimize the following problem: You have a data frame with 2 columns. data.input= data.frame(state1 = (1:500), state2 = (201:700) ) with data that partially overlap in terms of values. I want to minimize the assessment error of each state by using this function: err.th.scalar <- function(threshold, data){ state1 <- data$state1 state2 <- data$state2

On 01/24/2011 04:41 AM, Douglas do Couto Teixeira wrote: > Hi, > > Nick, thanks for the reply. > I still have a problem: I only need to "clone" an Instruction, changing > its type. That is, I would like to keep all characteristics of the old > Instruction and create a new one only with a different type. Sure, but what about its operands? An "add" instruction

On 1 Oct 2010, at 13:35, Bill Wendling wrote: > On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > >> Bill Wendling wrote: >>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >>> >>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>>> >>>>> Our architecture has 1-bit boolean predicate registers. >>>>>

I'm currently trying to get llvm-mc --disassemble working for the XCore backend. Up until recently there was no instruction encoding / decoding information on any of the XCore instructions so Im incrementally adding this information at the same time as adding tests for the disassembler. However I've run into a problem and I'm not sure of the best way to solve it. With some of the

Bill Wendling wrote: > On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > >> Bill Wendling wrote: >>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >>> >>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>>> >>>>> Our architecture has 1-bit boolean predicate registers. >>>>> >>>>> I've

The documentation of LLVM says that "The llvm.objectsize intrinsic is lowered to a constant representing the size of the object concerned". I'm attempting to lower this intrinsic function to a constant in a pass. Below is the code snippet that I wrote: for (BasicBlock::iterator i = b.begin(), ie = b.end(); (i != ie) && (block_split == false);) { IntrinsicInst *ii =

Dear All, The InstCombine pass performs the following transformation. Z / (X / Y) => (Y * Z) / X This is performed only when operand Op1 ( (X/Y) in this case) has only one use in future. The code snippet is shown below. if (match(Op1, m_OneUse(m_FDiv(m_Value(X), m_Value(Y)))) && (!isa<Constant>(Y) || !isa<Constant>(Op0))) { // Z / (X / Y) => (Y *