similar to: Loops

Hi. Can anyone suggest a simple way to obtain in R a list of vector coordinates of the following form? The code below is Mathematica. In[5]:= Flatten[Table[{i,j,k},{i,3},{j,4},{k,5}], 2] Out[5]= {{1,1,1},{1,1,2},{1,1,3},{1,1,4},{1,1,5},{1,2,1},{1,2,2},{1,2,3},{1 ,2,4},{1,2, 5},{1,3,1},{1,3,2},{1,3,3},{1,3,4},{1,3,5},{1,4,1},{1,4,2},{1,4,3}, {1,4,

Hi, I am trying to use rsync to migrate homefolders from one server to another. For this I use: > rsync --rsh="ssh -l root" -vaz beaucent.ling.umu.se:/export/home/ . Which works fine until I get to some files where the user has, unfortunatelly, used a non-ascii character in the file name: --- snip -- ...

Hi all I didn't find anything relevant in the archives about this so I wanted to ask here. I am generating a simple function for JIT using the API. The function structure and code work fine with 2.8 but give me "Cannot select" with 2.9. Assembly dump of the function: define double @0(double %f0, double %f1, double %f2, double %f3, double %f4, double %f5, double %f6, double %f7,

Hi there, I'm having a hard time with promoting operands from i1 to i32 in my backend... I have to register classes, VTs are i1 and i32. The i1 registers are only for predication and conditional jumps, so I want to use them with brcond, setcc. There are no instructions to directly load a value in an i1 register or to copy between i1 and i32, so I need the DAG Legalizing Pass to not generate

Hi all,�� � I am new to llvm. I need help. Thank you every! � � I want to realize vcvtt.f16.f32 �NEON instruction by llvm. This instruction covert top-16bits of a single type to f16. I use the intrinsics function llvm.convert.to.fp16, but cannot llc ,�I meet is following problem : LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] 0x9fc0750: f32,ch = load 0x3aafd68,

Hi all, This is Linfeng Zhang from Google. I'll work on ARM NEON optimization in the next few months. I'm submitting 2 patches in the following couple of emails, which have the new created celt_fir_neon(). I revised celt_fir_c() to not pass in argument "mem" in Patch 1. If there are concerns to this change, please let me know. Many thanks to your comments. Linfeng Zhang

    Thank you Kevin!!!    If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, "fptrunc  double %tmp to float" is right, but "fptrunc float %tmp to half" is wrong). My target platform is MIPS.  The command as following: NEON:            vcvtt.f16.f32 s2, s0 llvm Code: %Vt_2 = load float* %VFP_s0, align 4 %Vt3_1 = fptrunc float %Vt_2 to half %Vt4_1 = bitcast half

On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote: > > On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote: > > > Here's my "thought experiment" (from PR11589): I have a bunch of > > load-fadd-store chains to schedule. A store takes two cycles to > > clear > > its last pipeline stage. The fadd takes longer to compute its result > > (say 5

On Thu, Mar 17, 2016 at 2:41 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > On Thu, Mar 17, 2016 at 10:10 AM, Rail Shafigulin <rail at esenciatech.com> > wrote: > >> On Wed, Mar 16, 2016 at 6:38 PM, Mehdi Amini <mehdi.amini at apple.com> >> wrote: >> >>> >>> On Mar 16, 2016, at 5:38 PM, Rail Shafigulin <rail at

Hi Daniel,    Thank you your replying.     Yes, the problem is about MIPS backend. You give me this message "There is limited support for the <8 x f16> type when MSA (MIPS SIMD Architecture) is enabled but even then scalar half-precision is not currently supported."  Could you give me some official link or some evidence? Thank you very much. Robin yalong at multicorewareinc.com

Dear all, I am still a R apprentice... Apologies for the basic question. I am trying to reshape a dataframe based on the order of two variables (a character variable and a numerical variable). To simplify it, consider the following dataframe > df<-data.frame(id=c("b","b","a","a","a"),ord=c(2,1,1,3,2)) id ord 1 b 2 2 b 1 3 a 1 4

Hi all - I'm trying to generate lattice barchart graphs with missing values, and came across the following: This does not run. I would expect it to: library(lattice) D = data.frame(X=1, Y=factor(letters[2], letters[1:2])) barchart(~ X, D, groups=Y) Error in grid.Call.graphics("L_rect", x$x, x$y, x$width, x$height, resolveHJust(x$just, : invalid line type which is simply

On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote: > Here's my "thought experiment" (from PR11589): I have a bunch of > load-fadd-store chains to schedule. A store takes two cycles to clear > its last pipeline stage. The fadd takes longer to compute its result > (say 5 cycles), but can sustain a rate of 1 independent add per cycle. > As the scheduling is bottom-up, it

On 07/09/2014 12:41 PM, Matt Arsenault wrote: > On 07/09/2014 03:30 PM, yalong at multicorewareinc.com wrote: >> Thank you Kevin!!! >> If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, >> "fptrunc double %tmp to float" is right, but "fptrunc float %tmp to >> half" is wrong). My target platform is MIPS. The command as following:

On Tue, 2011-12-20 at 10:35 -0600, Hal Finkel wrote: > On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote: > > > > On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote: > > > > > Here's my "thought experiment" (from PR11589): I have a bunch of > > > load-fadd-store chains to schedule. A store takes two cycles to > > > clear > >

I'm trying to figure out how to interpret DAG output that is shown below. If I were to draw it by hand, how would I do it? I tried to do it, but unfortunately I can't figure it out. I know there is a way to generate a graph, but I made some changes to my backend which hangs clang/llc. Would someone be kind enough to give a picture of what of a graph below? I'm sure once I see one I

Hi everyone, I have the following code (as part of a larger function): %0 = icmp eq i16 %a, 0 ; <i1> [#uses=1] br i1 %0, label %bb1, label %bb I would like to match this with a BRCOND, but all I get is an error message when compiling the above code that say: LLVM ERROR: Cannot yet select: 0x170f200: ch = br_cc 0x170f000, 0x170ed00, 0x170dc60, 0x170ec00, 0x170ef00 [ID=19]

On Dec 20, 2011, at 10:29 AM, Hal Finkel wrote: > On Tue, 2011-12-20 at 10:35 -0600, Hal Finkel wrote: >> On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote: >>> >>> On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote: >>> >>>> Here's my "thought experiment" (from PR11589): I have a bunch of >>>> load-fadd-store chains to

Hello, I am new to LLVM and doing some experiment with 3.2 on Ada code. Can anyone help me on the following error message? Thanks, ZY LLVM ERROR: Cannot select: 0xa7a0bf0: f32 = truncate 0xa7a5ea8 [ID=24] 0xa7a5ea8: i32 = X86ISD::SHLD 0xa790280, 0xa790390, 0xa76e088 [ID=22] 0xa790280: i32,ch = load 0xa7386a0, 0xa7a68d8, 0xa7a5628<LD1[%1482+4], anyext from i8> [ID=19]

On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > >> Our architecture has 1-bit boolean predicate registers. >> >> I've defined comparison >> >> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;