similar to: Reshape dataframe according to ordered variables

Hello all, As an example, consider the following dataframe > df<-data.frame(id=c("b","b","a","a","a"),ord=c(2,1,1,3,2)) > dates<-as.Date(c("02/27/92", "02/27/92", "01/14/92", "02/28/92", "02/01/92"),"%m/%d/%y") > df$dates<-dates which was ordered with >

Hello all, I am trying to do a Latin Hypercube Sampling (LHS) to a 5-parameter design matrix. I start as follows: library(lhs) p1<-randomLHS(1000, 5) If I check the distribution of each parameter (column), they are perfectly uniformly distributed (as expected).For example, hist(p1[,1]) Now the hard (maybe strange) question. I want the combination of the first three parameters to sum up to

Hello all, Can someone tell me why the following mixture of two log-normal distributions does not get truncated? What puzzles me is that the function works almost always, but for certain combinations (like the one below), it does not. # R code example library(distr) mix<-UnivarMixingDistribution(Lnorm(3.2,0.5),Lnorm(5.4,0.6),mixCoeff=c(0.3,0.7))

Hello all, This shouldn't be difficult, but I am not able to extract a printed value from a function and assign it to an object. In my case, > library(DAAG) > twotPermutation(c(2,3,4),c(3,6,5),plotit=F) [1] 0.298 I would like to assign this result to an object. Thanks, Duarte

Hi all I didn't find anything relevant in the archives about this so I wanted to ask here. I am generating a simple function for JIT using the API. The function structure and code work fine with 2.8 but give me "Cannot select" with 2.9. Assembly dump of the function: define double @0(double %f0, double %f1, double %f2, double %f3, double %f4, double %f5, double %f6, double %f7,

Hi there, I'm having a hard time with promoting operands from i1 to i32 in my backend... I have to register classes, VTs are i1 and i32. The i1 registers are only for predication and conditional jumps, so I want to use them with brcond, setcc. There are no instructions to directly load a value in an i1 register or to copy between i1 and i32, so I need the DAG Legalizing Pass to not generate

Dear all, I do not seem to grasp how contrasts are set for ordered factors. Perhaps someone can elighten me? When I work with ordered factors, I would often like to be able to reduce the used polynomial to a simpler one (where possible). Thus, I would like to explicetly code the polynomial but ideally, the intial model (thus, the full polynomial) would be identical to one with an ordered factor.

Hi all,�� � I am new to llvm. I need help. Thank you every! � � I want to realize vcvtt.f16.f32 �NEON instruction by llvm. This instruction covert top-16bits of a single type to f16. I use the intrinsics function llvm.convert.to.fp16, but cannot llc ,�I meet is following problem : LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] 0x9fc0750: f32,ch = load 0x3aafd68,

On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote: > > On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote: > > > Here's my "thought experiment" (from PR11589): I have a bunch of > > load-fadd-store chains to schedule. A store takes two cycles to > > clear > > its last pipeline stage. The fadd takes longer to compute its result > > (say 5

    Thank you Kevin!!!    If I use fptrunc and bitcast realise NEON vcvtt ( I can sure, "fptrunc  double %tmp to float" is right, but "fptrunc float %tmp to half" is wrong). My target platform is MIPS.  The command as following: NEON:            vcvtt.f16.f32 s2, s0 llvm Code: %Vt_2 = load float* %VFP_s0, align 4 %Vt3_1 = fptrunc float %Vt_2 to half %Vt4_1 = bitcast half

On Thu, Mar 17, 2016 at 2:41 PM, Rail Shafigulin <rail at esenciatech.com> wrote: > On Thu, Mar 17, 2016 at 10:10 AM, Rail Shafigulin <rail at esenciatech.com> > wrote: > >> On Wed, Mar 16, 2016 at 6:38 PM, Mehdi Amini <mehdi.amini at apple.com> >> wrote: >> >>> >>> On Mar 16, 2016, at 5:38 PM, Rail Shafigulin <rail at

On Tue, 2011-12-20 at 10:35 -0600, Hal Finkel wrote: > On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote: > > > > On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote: > > > > > Here's my "thought experiment" (from PR11589): I have a bunch of > > > load-fadd-store chains to schedule. A store takes two cycles to > > > clear > >

Dear forum, I would like to forecast e.g. with the arima-model. To figure out which model works best I am going to predict with this models. my first code: for(ar.ord in 1:3){ for(ma.ord in 1:3){ print(predict(arima(para_qtr[1:(n-8),1],order=c(ar.ord,1,ma.ord)), n.ahead=8)$pred) } } this one works. but I want to "save" my results in a matrix or a data.frame. my second code:

Hi Daniel,    Thank you your replying.     Yes, the problem is about MIPS backend. You give me this message "There is limited support for the <8 x f16> type when MSA (MIPS SIMD Architecture) is enabled but even then scalar half-precision is not currently supported."  Could you give me some official link or some evidence? Thank you very much. Robin yalong at multicorewareinc.com

I'm trying to figure out how to interpret DAG output that is shown below. If I were to draw it by hand, how would I do it? I tried to do it, but unfortunately I can't figure it out. I know there is a way to generate a graph, but I made some changes to my backend which hangs clang/llc. Would someone be kind enough to give a picture of what of a graph below? I'm sure once I see one I

Hi everyone, I have the following code (as part of a larger function): %0 = icmp eq i16 %a, 0 ; <i1> [#uses=1] br i1 %0, label %bb1, label %bb I would like to match this with a BRCOND, but all I get is an error message when compiling the above code that say: LLVM ERROR: Cannot yet select: 0x170f200: ch = br_cc 0x170f000, 0x170ed00, 0x170dc60, 0x170ec00, 0x170ef00 [ID=19]

On Dec 20, 2011, at 10:29 AM, Hal Finkel wrote: > On Tue, 2011-12-20 at 10:35 -0600, Hal Finkel wrote: >> On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote: >>> >>> On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote: >>> >>>> Here's my "thought experiment" (from PR11589): I have a bunch of >>>> load-fadd-store chains to

I'm trying to create a TableGen pattern to match extract_vector_elt. My pattern looks like this: (set i32:$dest, (extract_vector_elt v16i32:$src, i32:$index)) However, when I compile, I get an error: error: Variable not defined: 'extract_vector_elt' However, if I omit the rule and attempt to compile something that uses this functionality with clang, I get this error, which

Hello, I am new to LLVM and doing some experiment with 3.2 on Ada code. Can anyone help me on the following error message? Thanks, ZY LLVM ERROR: Cannot select: 0xa7a0bf0: f32 = truncate 0xa7a5ea8 [ID=24] 0xa7a5ea8: i32 = X86ISD::SHLD 0xa790280, 0xa790390, 0xa76e088 [ID=22] 0xa790280: i32,ch = load 0xa7386a0, 0xa7a68d8, 0xa7a5628<LD1[%1482+4], anyext from i8> [ID=19]

Bill Wendling wrote: > On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > >> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >> >>> Our architecture has 1-bit boolean predicate registers. >>> >>> I've defined comparison >>> >>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set