similar to: stochastic process

Displaying 20 results from an estimated 1000 matches similar to: "stochastic process"

2009 Mar 31
1
[LLVMdev] 转发: Re: Dear Evan Chang, Re: help: about how to use tblgen to constraint operand.
Dear Evan Chang: I register incorrect Register class for MVT::f64. I have fixed it. Thanks your advice. "-view-legalize-dags" is very good option. But I don't know why my LLC do not know " -view-legalize-type-dags" option. By the way, I use llvm 2.5 merged from llvm2.4. Best Regards, Ren Kun --- 09年3月31日,周二, Evan Cheng <echeng at apple.com> 写道: 发件人: Evan Cheng
2007 Nov 16
1
Efficient way to compute power of a sparse matrix
Dear all, I would like to compute power of a square non symmetric matrix. This is a part of a simulation study. Matrices are quite large (e.g., 900 by 900), and contains many 0 (more than 99 %). I have try the function mtx.exp of the Biodem package: library(Biodem) m <- matrix(0, 900, 900) i <- sample(1:900, 3000, replace = T) j <- sample(1:900, 3000, replace = T) for(x in 1:3000)
2009 Mar 30
1
[LLVMdev] Dear Evan Chang, Re: help: about how to use tblgen to constraint operand.
I try to define a register class def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] to simulate even/odd pair of GPR32 register. Actually, I just use GPR64 as a temporary register. My CPU just support i32 Integer type directly. I use FDR to save f64. def FDR : RegisterClass<"mytarget", [f64], 64,[FD0, FD1, ....] When I move f64 to even/odd pair register, I
2009 Feb 20
0
[LLVMdev] help: about how to use tblgen to constraint operand.
On Feb 19, 2009, at 8:26 PM, 任坤 wrote: > hi, Dear Evan Cheng: > > My cpu is i32 embeded CPU. I define pseudo register pair registers. > > In mytargetRegisterInfo.td: > def T0: RegisterWithSubRegs<"t0",[R0,R1]>; > ... > def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] > > In mytargetISelLowering.cpp: > I define i1, i8 ,
2009 Feb 20
2
[LLVMdev] help: about how to use tblgen to constraint operand.
hi, Dear Evan Cheng: My cpu is i32 embeded CPU. I define pseudo register pair registers. In mytargetRegisterInfo.td: def T0: RegisterWithSubRegs<"t0",[R0,R1]>; ... def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] In mytargetISelLowering.cpp: I define i1, i8 , i16 and i32 are legal. 1. I still have problem. I save my function return double  value in
2009 Dec 04
4
[LLVMdev] hi, Hi, (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really?
Hi, EveryOne: I am travelling CFG with MachineFunction. So I want to sure it. (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really? best regards. ___________________________________________________________ 好玩贺卡等你发,邮箱贺卡全新上线! http://card.mail.cn.yahoo.com/ -------------- next part -------------- An HTML attachment was scrubbed...
2009 Jan 04
2
[LLVMdev] hi, llvm-gcc deal with va_arg() by word alignment.
hi,      I am porting llvm to our embedded cpu. By my abi, long long type is aligned by 8 bytes. But now llvm-gcc frontend follows x86 abi, generate word-alignment LLVM-IR for va_arg().    In some degree, llvm-gcc frontend depends on targets. The best solution is llvm-gcc can create va_arg node, I can lower it at the backend.    Who can give a temporary solution to make frontend can create 8
2009 Feb 19
1
[LLVMdev] help: about how to use tblgen to constraint operand.
I define a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr. But I need to use an even/odd register pair to save its 2 operands. I define in mytarget.td: myfmdrr: SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,     SDTCisSameAs<1, 2>]>; def my_fmdrr : ........... def myFMDRR : ....                       (outs FPR: $result), ins(GPR:
2010 Jan 25
2
[LLVMdev] Find all backedges of CFG by MachineDominatorTree. please look at my jpg.
Hi: I hope to cut all backedges of MachineFunction CFG, then topological sort MachineBasicBlocks. 1. MachineDominatorTree *domintree = new MachineDominatorTree(); domintree->runOnMachineFunction(mf); 2. Then travel mf one by one. When domintree->dominates(next,current) is true, there is a backedge from current node to next node. move this backedge form CFG. But I find A LOOP in
2005 Apr 18
1
Rd.sty problems.
Hi All, I am trying to build a new R package to submit, but it's failing to create a tex manual: R CMD check Biodem * checking for working latex ... OK * using log directory '/home/greatsage/Fede/R-packages/temp/Biodem.Rcheck' * checking for file 'Biodem/DESCRIPTION' ... OK * checking if this is a source package ... OK * Installing *source* package 'Biodem' ... ** R
2009 Sep 23
2
[LLVMdev] About porting llvm-gcc frontend.
I am porting llvm-gcc frontend. We have ported GCC4.2 for our target. So I move *.h *.md and *.c to llvm-gcc.  I do not implement any LLVM MACRO, and use default action of llvm-gcc.  I get a new llvm-gcc for our target. But I get a bug. /******************************/ //#include <stdio.h> union MYunion {   unsigned char uc ;   int ui; } myunion; void vfu1(union MYunion  u) {     u.ui =
2010 Jan 15
2
[LLVMdev] <IsKill> getting from MachineOperand is just <Used> attribute from logic.
Hi, I have ported LLC to a risc cpu. It can pass benchmark that I have at current. But I want do some optimization after register alloction by adjusting register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. R4 is marked <kill> at MBB0. If I scan R4's
2009 Apr 22
0
[LLVMdev] a very strange question about adding new instrinsic.
Hi: I want add new Instrinsic for my target. So I first do some test. I add them in IntrinsicsPowerPC.td //===--------------------===// let TargetPrefix = "ppc" in { def int_ppc_mytest : Intrinsic<[llvm_void_ty], [], [IntrWriteMem]>; } //===--------------------===// I add them in PPCInstrInfo.td //===--------------------===// def MYTEST : XForm_24_sync<31, 599, (outs), (ins),
2010 Jan 25
0
[LLVMdev] About MachineDominatorTree Pass.
Hi: I hope to cut all backedges of MachineFunction CFG, then topological sort MachineBasicBlocks. 1. MachineDominatorTree *domintree = new MachineDominatorTree(); domintree->runOnMachineFunction(mf); 2. Then travel mf one by one. When domintree->dominates(next,current) is true, there is a backedge from current node to next node. move this backedge form CFG. But I find A LOOP in
2010 Jan 26
1
[LLVMdev] Find all backedges of CFG by MachineDominatorTree. please look at my jpg.
Hi, Dear Boissinot: 1. When I have irreducible CFG, I travel its nodes by DFS. search backedge for every node. After I finish one node, push it into a stack. [0, 1, 2, M] <---push. [0, 1, 2, M,...N] <---push. When resolving node M, find a edge from node N to node M, N is not in stack(M < N), It is a backedge. N is in stack(M > N), It is NOT a backedge.
2009 Jun 26
0
calculate AIC
Dear all,   I want to calculate AIC values of PLSR models. But I find that AIC and extractAIC functions in R could not be used to calculate AIC values of PLSR models. Now I write a section of code(below) to calculate it. But I don't known whether the result is right or not. If I am wrong, please give me some suggestions. Thanks a lot.   Rong Huang   data<-data.frame(
2005 Apr 24
1
Biodem 0.1/orphaning of MAlmig
Together with Alessio Boattini of the University of Bologna we have created a package called Biodem. Biodem provides a number of functions for Biodemographycal analysis, and we hope it will be useful to the anthropological community. Because Biodem contains all the functions found in Malmig (a package I maintain), I would like to orphan it, or, even better, have it removed from CRAN. Finally,
2005 Apr 24
1
Biodem 0.1/orphaning of MAlmig
Together with Alessio Boattini of the University of Bologna we have created a package called Biodem. Biodem provides a number of functions for Biodemographycal analysis, and we hope it will be useful to the anthropological community. Because Biodem contains all the functions found in Malmig (a package I maintain), I would like to orphan it, or, even better, have it removed from CRAN. Finally,
2012 Jan 30
1
Quantum scalar i40 tape partitions
Hi All, I have a Quantum scalar i40 tape library. I need to configure it to TWO tape partition libraries, e.g., library_a and library_b, so that each library has its own tape drive. Then connect this physical tape library to two different CentOS servers so that each server can see its own media changer and tape drive. I once had a successful configuration on one host but NOT on the other. One
2004 Nov 25
4
Avoiding for-loops
Hello R-users, I have a symmetric matrix of numerical values and I want to obtain those values in the upper or lower triangle of the matrix in a vector. I tried to do the job by using two for-loops but it doens't seem to be a clever way, and I'd like to know a more efficient code for a large matrix of thousands of rows and columns. Below is my code for your reference. Thanks a lot.