[llvm-dev] Defining instruction aliases

David Greene via llvm-dev
Mon, 17 Jan 2022 19:10:48 -0000

Hey everyone,

We've defined some instruction aliases for our target but are having
trouble with the assembler.  According to the documentation
(https://llvm.org/docs/CodeGenerator.html#instruction-aliases) LLVM has
the capability of defining aliases with different kinds of operands.  We
use that capability to define, for example, different alises based on
the kind of immediate seen.

However, it seems that the generated assembler can't distinguish these
different kinds of immediates and ends up encoding the wrong operation,
leading to incorrect assembly.

Is this a known limitation?  Are we perhaps missing some option to the
InstAlias class (UseInstAsmMatchConverter?), some option to TableGen or
perhaps we can add some custom code to pick the right MC instruction?

I'm thinking AsmMatchConverter might be what we need but a quick search
didn't locate any documentation of what this is and how to use it.

Thanks in advance for the help!

David
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