[llvm-dev] TableGen boolean literals: opinions, please

Thomas Lively via llvm-dev
Thu, 22 Oct 2020 02:10:00 -0000

Even given the option to use TRUE and FALSE, I think I would prefer to
continue using 1 and 0 for stylistic reasons. Most of the TableGen I work
with is snake_case or CamelCase, so all-caps TRUE and FALSE would look out
of place. If we could use lower case `true` and `false`, I would use those.

On Wed, Oct 21, 2020 at 6:10 PM Chris Lattner via llvm-dev <
llvm-dev at lists.llvm.org> wrote:

>
>
> > On Oct 21, 2020, at 9:20 AM, Paul C. Anagnostopoulos via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
> >
> > I need opinions from active TableGen users.
> >
> > Does it make sense to add 'true' and 'false' boolean
literals to
> TableGen, for use in assigning values to bit fields? If so, they would be
> TRUE and FALSE.
> >
> > A search of all the TableGen files finds no use of TRUE or FALSE
except
> in tests.
>
> You’re thinking about something like “bit x = TRUE;” instead of “bit x >
1;”?  Is there an advantage to that spelling?
>
> -Chris
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20201021/b48f35e9/attachment.html>