[llvm-dev] Questions about vscale

Chris Tetreault via llvm-dev
Tue, 07 Apr 2020 16:38:37 -0000

Hi,

    Looking at the language reference, vscale is an integer. This might pose a
problem for fractional vscale. Furthermore, I believe that vscale is constant
throughout the life of the program; so if RISC-V vscale can vary from
instruction to instruction that may also be problematic unless you can just
commit to one specific value of vscale.

   Also, I had a question about your table. Based on your description of how
LMUL works, I’d expect that LMUL == vscale, and that each column in your table
would be the same:




int64_t | vscale x 1 x i64

int32_t | vscale x 2 x i32

int16_t | vscale x 4 x i16
 int8_t | vscale x 8 x i8

… which is basically equivalent to:


int64_t | LMUL x 1 x i64

int32_t | LMUL x 2 x i32

int16_t | LMUL x 4 x i16
 int8_t | LMUL x 8 x i8


… is this not the case?

Thanks,
   Chris Tetreault

From: llvm-dev <llvm-dev-bounces at lists.llvm.org<mailto:llvm-dev-bounces
at lists.llvm.org>> On Behalf Of Kai Wang via llvm-dev
Sent: Tuesday, April 7, 2020 1:31 AM
To: llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>
Cc: Roger Ferrer Ibanez <roger.ferrer at bsc.es<mailto:roger.ferrer at
bsc.es>>; rengolin at gmail.co<mailto:rengolin at gmail.co>;
robin.kruppe at gmail.com<mailto:robin.kruppe at gmail.com>
Subject: [EXT] [llvm-dev] Questions about vscale


Hi,



In RISC-V v-extension, operations could operate on a group of vector registers;
we called it LMUL. If LMUL equals 2, it means we could operate on 2 vector
registers at the same time. So, we have the following combinations of types.



          LMUL = 1           LMUL = 2            LMUL = 4            LMUL = 8

int64_t | vscale x 1 x i64 | vscale x  2 x i64 | vscale x  4 x i64 | vscale x  8
x i64

int32_t | vscale x 2 x i32 | vscale x  4 x i32 | vscale x  8 x i32 | vscale x 16
x i32

int16_t | vscale x 4 x i16 | vscale x  8 x i16 | vscale x 16 x i16 | vscale x 32
x i16

 int8_t | vscale x 8 x i8  | vscale x 16 x i8  | vscale x 32 x i8  | vscale x 64
x i8



We have another architecture parameter, ELEN, which means the maximum size of a
single vector element in bits.

We hope the type system could be consistent under ELEN = 32 and ELEN = 64.
However, vscale may be a fractional value under ELEN = 32 in the above type
system. When ELEN = 32, i64 is an invalid type (we could ignore the first row
for ELEN = 32) and vscale may become 1/2 on run time to fit the architecture (if
the vector register only has 32 bits). Is there any problem to assume vscale to
be fractional under some circumstances? vscale should be an unknown value when
compiling. So, it should have no impact on code generation and optimization. The
relationship between types is correct regardless vscale’s value. Is there
anything I missed?



Thanks!

Hsiangkai
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