[llvm-dev] Tablegen PAT limitation?

Celine via llvm-dev
Thu, 21 Nov 2019 12:58:11 -0000

Hi Pete,


I tried it on LLVM 9.0.0 + git master patch show below, Still the same issue :(


--- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -501,7 +501,7 @@ bool TypeInfer::EnforceSmallerThan(TypeSetByHwMode
&amp;Small,
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; berase_if(B, isVector);
&nbsp; &nbsp; &nbsp;}
&nbsp; &nbsp;}
-
+#if 0
&nbsp; &nbsp;auto LT = [](MVT A, MVT B) -&gt; bool {
&nbsp; &nbsp; &nbsp;return A.getScalarSizeInBits() <
B.getScalarSizeInBits() ||
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
(A.getScalarSizeInBits() == B.getScalarSizeInBits() &amp;&amp;
@@ -516,7 +516,22 @@ bool TypeInfer::EnforceSmallerThan(TypeSetByHwMode
&amp;Small,
&nbsp; &nbsp; &nbsp;return LT(A, B) || (A.getScalarSizeInBits() ==
B.getScalarSizeInBits() &amp;&amp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp;A.getSizeInBits() == B.getSizeInBits());
&nbsp; &nbsp;};
+#else
+&nbsp; auto LT = [](MVT A, MVT B) -&gt; bool {
+&nbsp; &nbsp; return A.getScalarSizeInBits() <
B.getScalarSizeInBits() ||
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp;(A.getScalarSizeInBits() == B.getScalarSizeInBits() &amp;&amp;
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
A.getSizeInBits() < B.getSizeInBits());
+&nbsp; };
+&nbsp; auto LE = [&amp;LT](MVT A, MVT B) -&gt; bool {
+&nbsp; &nbsp; // This function is used when removing elements: when a
vector is compared
+&nbsp; &nbsp; // to a non-vector, it should return false (to avoid
removal).
+&nbsp; &nbsp; if (A.isVector() != B.isVector())
+&nbsp; &nbsp; &nbsp; return false;
&nbsp;
+&nbsp; &nbsp; return LT(A, B) || (A.getScalarSizeInBits() ==
B.getScalarSizeInBits() &amp;&amp;
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; A.getSizeInBits() ==
B.getSizeInBits());
+&nbsp; };
+#endif
&nbsp; &nbsp;for (unsigned M : Modes) {
&nbsp; &nbsp; &nbsp;TypeSetByHwMode::SetType &amp;S =
Small.get(M);
&nbsp; &nbsp; &nbsp;TypeSetByHwMode::SetType &amp;B =
Big.get(M);











------------------&nbsp;Original&nbsp;------------------
From:&nbsp;"Pete Couperus"<Peter.J.Couperus at
synopsys.com&gt;;
Date:&nbsp;Thu, Nov 21, 2019 03:36 AM
To:&nbsp;"Celine"<595602881 at qq.com&gt;;"Krzysztof
Parzyszek"<kparzysz at quicinc.com&gt;;"llvm-dev at
lists.llvm.org"<llvm-dev at lists.llvm.org&gt;;

Subject:&nbsp;RE: [llvm-dev] Tablegen PAT limitation?




Hi Celine,

&nbsp;

What LLVM version is this, and does it reproduce with the trunk?

I ran into a weird issue with this signature a few months back, and it turned
out to be a bug in how tblgen eliminated types when inferring patterns:

https://reviews.llvm.org/D61705

&nbsp;

If this is reproducible on trunk with some easy to apply patch, I could take a
look?

&nbsp;

Pete

&nbsp;

&nbsp;

From: llvm-dev <llvm-dev-bounces at lists.llvm.org&gt; On Behalf Of
Celine via llvm-dev
 Sent: Tuesday, November 19, 2019 8:07 PM
 To: Krzysztof Parzyszek <kparzysz at quicinc.com&gt;; llvm-dev
<llvm-dev at lists.llvm.org&gt;
 Subject: Re: [llvm-dev] Tablegen PAT limitation?

&nbsp;

Hi,


&nbsp;


The full trace stack:


Type set is empty for each HW mode:


possible type contradiction in the pattern below (use -print-records with
llvm-tblgen to see all expanded records).


vtInt: &nbsp; &nbsp; (vt:{ *:[Other] })


UNREACHABLE executed at
/home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!


[ 85%] Building X86GenEVEX2VEXTables.inc...


&nbsp;#0 0x000000000081b9b5
llvm::sys::PrintStackTrace(llvm::raw_ostream&amp;)
/home/nancy/work/rpp_clang/llvm/lib/Support/Unix/Signals.inc:495:0


&nbsp;#1 0x000000000081ba48 PrintStackTraceSignalHandler(void*)
/home/nancy/work/rpp_clang/llvm/lib/Support/Unix/Signals.inc:559:0


&nbsp;#2 0x0000000000819602 llvm::sys::RunSignalHandlers()
/home/nancy/work/rpp_clang/llvm/lib/Support/Signals.cpp:69:0


&nbsp;#3 0x000000000081b3b0 SignalHandler(int)
/home/nancy/work/rpp_clang/llvm/lib/Support/Unix/Signals.inc:358:0


fcdsaa #4 0x00007f16408a6390 __restore_rt
(/lib/x86_64-linux-gnu/libpthread.so.0+0x11390)


&nbsp;#5 0x00007f163fa36428 gsignal
/build/glibc-LK5gWL/glibc-2.23/signal/../sysdeps/unix/sysv/linux/raise.c:54:0


&nbsp;#6 0x00007f163fa3802a abort
/build/glibc-LK5gWL/glibc-2.23/stdlib/abort.c:91:0


&nbsp;#7 0x0000000000797d00 bindingsErrorHandler(void*,
std::__cxx11::basic_string<char, std::char_traits<char&gt;,
std::allocator<char&gt; &gt; const&amp;, bool)
/home/nancy/work/rpp_clang/llvm/lib/Support/ErrorHandling.cpp:231:0


&nbsp;#8 0x00000000004838a8
llvm::TypeInfer::ValidateOnExit::~ValidateOnExit()
/home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:826:0


&nbsp;#9 0x00000000004808bd
llvm::TypeInfer::EnforceSmallerThan(llvm::TypeSetByHwMode&amp;,
llvm::TypeSetByHwMode&amp;)
/home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:455:0


#10 0x000000000048860f
llvm::SDTypeConstraint::ApplyTypeConstraint(llvm::TreePatternNode*,
llvm::SDNodeInfo const&amp;, llvm::TreePattern&amp;) const
/home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:1506:0


#11 0x00000000004a780b
llvm::SDNodeInfo::ApplyTypeConstraints(llvm::TreePatternNode*,
llvm::TreePattern&amp;) const
/home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.h:1307:0


#12 0x000000000048e303
llvm::TreePatternNode::ApplyTypeConstraints(llvm::TreePattern&amp;, bool)
/home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2362:0


#13 0x000000000048e2d4
llvm::TreePatternNode::ApplyTypeConstraints(llvm::TreePattern&amp;, bool)
/home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2361:0


#14 0x000000000048e2d4
llvm::TreePatternNode::ApplyTypeConstraints(llvm::TreePattern&amp;, bool)
/home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2361:0


#15 0x000000000048e2d4
llvm::TreePatternNode::ApplyTypeConstraints(llvm::TreePattern&amp;, bool)
/home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:2361:0


#16 0x00000000005b3c06 (anonymous
namespace)::MatcherGen::InferPossibleTypes(unsigned int)
/home/nancy/work/rpp_clang/llvm/utils/TableGen/DAGISelMatcherGen.cpp:184:0


#17 0x00000000005b59ca (anonymous
namespace)::MatcherGen::EmitMatchCode(llvm::TreePatternNode const*,
llvm::TreePatternNode*, unsigned int)
/home/nancy/work/rpp_clang/llvm/utils/TableGen/DAGISelMatcherGen.cpp:491:0


#18 0x00000000005b54ba (anonymous
namespace)::MatcherGen::EmitOperatorMatchCode(llvm::TreePatternNode const*,
llvm::TreePatternNode*, unsigned int)
/home/nancy/work/rpp_clang/llvm/utils/TableGen/DAGISelMatcherGen.cpp:440:0


#19 0x00000000005b5c9c (anonymous
namespace)::MatcherGen::EmitMatchCode(llvm::TreePatternNode const*,
llvm::TreePatternNode*, unsigned int)
/home/nancy/work/rpp_clang/llvm/utils/TableGen/DAGISelMatcherGen.cpp:515:0


#20 0x00000000005b6271 (anonymous
namespace)::MatcherGen::EmitMatcherCode(unsigned int)
/home/nancy/work/rpp_clang/llvm/utils/TableGen/DAGISelMatcherGen.cpp:559:0


#21 0x00000000005b8f4a llvm::ConvertPatternToMatcher(llvm::PatternToMatch
const&amp;, unsigned int, llvm::CodeGenDAGPatterns const&amp;)
/home/nancy/work/rpp_clang/llvm/utils/TableGen/DAGISelMatcherGen.cpp:1026:0


#22 0x000000000059db91 (anonymous
namespace)::DAGISelEmitter::run(llvm::raw_ostream&amp;)
/home/nancy/work/rpp_clang/llvm/utils/TableGen/DAGISelEmitter.cpp:169:0


#23 0x000000000059dd1b llvm::EmitDAGISel(llvm::RecordKeeper&amp;,
llvm::raw_ostream&amp;)
/home/nancy/work/rpp_clang/llvm/utils/TableGen/DAGISelEmitter.cpp:187:0


#24 0x00000000007357d1 (anonymous
namespace)::LLVMTableGenMain(llvm::raw_ostream&amp;,
llvm::RecordKeeper&amp;)
/home/nancy/work/rpp_clang/llvm/utils/TableGen/TableGen.cpp:170:0


#25 0x000000000085c5b8 llvm::TableGenMain(char*, bool
(*)(llvm::raw_ostream&amp;, llvm::RecordKeeper&amp;))
/home/nancy/work/rpp_clang/llvm/lib/TableGen/Main.cpp:106:0


#26 0x0000000000735f0c main
/home/nancy/work/rpp_clang/llvm/utils/TableGen/TableGen.cpp:253:0


#27 0x00007f163fa21830 __libc_start_main
/build/glibc-LK5gWL/glibc-2.23/csu/../csu/libc-start.c:325:0


#28 0x0000000000407bd9 _start (../../../bin/llvm-tblgen+0x407bd9)



&nbsp;


&nbsp;


&nbsp;


==========================================================

PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } (shl:{ *:[v1i32] }
(sext:{ *:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] }
(imm:{ *:[i32] })<<P:Predicate_uimm2&gt;&gt;:$rshift)),
(bitconvert:{ *:[v1i32] } i32:{  *:[i32]
}:$rbase)))<<P:Predicate_unindexedstore&gt;&gt;<<P:Predicate_store&gt;&gt;


RESULT:&nbsp; (STOREbos v1i16:{ *:[v1i16] }:$rs1, i32:{ *:[i32] }:$rbase,
v1i16:{ *:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift)



&nbsp;


DAGIselMatcherGen.cpp: 559


Pattern.getSrcPattern()-&gt;dump();


//&nbsp; list<dag&gt; Pattern = [(store v1i16:$rs1, (add (v1i32
(bitconvert i32:$rbase)), (shl (v1i32 (sext v1i16:$roffset)), (v1i32
(build_vector uimm2:$rshift)))))];


&nbsp;


In CodeGenDAGPatterns.cpp: 1443


bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,


&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp;const SDNodeInfo &amp;NodeInfo,


&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp;TreePattern &amp;TP) const {



.....


N-&gt;dump() ; //&nbsp; (sext:{ *:[v1i32] } v1i16:{ *:[i16] }:$roffset)


Why it become v1i16:{ *:[i16] }:$roffset? Should be (sext:{ *:[v1i32] } v1i16:{
*:[v1i16] }:$roffset) as the Pattern defined.


&nbsp;


&nbsp; case SDTCisOpSmallerThanOp: {


&nbsp; &nbsp; unsigned BResNo = 0;


&nbsp; &nbsp; TreePatternNode *BigOperand

&nbsp; &nbsp; &nbsp;
getOperandNum(x.SDTCisOpSmallerThanOp_Info.BigOperandNum, N, NodeInfo,


&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; BResNo);


&nbsp;


NodeToApply-&gt;dump(); //v1i16:{ *:[i16] }:$roffset


BigOperand-&gt;dump();&nbsp; //(sext:{ *:[v1i32] } v1i16:{ *:[i16]
}:$roffset)



&nbsp;


&nbsp; &nbsp; return
TI.EnforceSmallerThan(NodeToApply-&gt;getExtType(ResNo),


&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp;BigOperand-&gt;getExtType(BResNo));


&nbsp; }




&nbsp;


bool TypeInfer::EnforceSmallerThan(TypeSetByHwMode &amp;Small,


&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp;TypeSetByHwMode &amp;Big) {



Small-&gt;dump(); //{ *:[i16] }


Big-&gt;dump(); // { *:[v1i32] }


....


&nbsp; &nbsp; if (none_of(S, isVector) || none_of(B, isVector)) {


&nbsp; &nbsp; &nbsp; Changed |= berase_if(S, isVector) |


&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp;berase_if(B, isVector);


&nbsp; &nbsp; }



Changed turn to True here which trigger the final error assert.


&nbsp;


How to understand Pattern Match process? Any document?


&nbsp;


------------------ Original ------------------


From:&nbsp;"Krzysztof Parzyszek"<kparzysz at
quicinc.com&gt;;


Date:&nbsp;Tue, Nov 19, 2019 10:09 PM


To:&nbsp;"Celine"<595602881 at qq.com&gt;;"llvm-dev at
lists.llvm.org"<llvm-dev at lists.llvm.org&gt;;


Subject:&nbsp;RE: [llvm-dev] Tablegen PAT limitation?



&nbsp;


Hi,

The problem is with a pattern that has a vt in it: the “vtInt …” printed below
the error message.&nbsp; Could you run llvm-tblgen from a debugger and show
the stack trace from where  the error occurred?

&nbsp;

--

Krzysztof Parzyszek kparzysz at quicinc.com&nbsp;&nbsp; AI tools
development

&nbsp;

From: llvm-dev <llvm-dev-bounces at lists.llvm.org&gt; On Behalf Of
Celine via llvm-dev
 Sent: Tuesday, November 19, 2019 6:52 AM
 To: llvm-dev <llvm-dev at lists.llvm.org&gt;
 Subject: [EXT] [llvm-dev] Tablegen PAT limitation?



&nbsp;

Hello,


&nbsp;


def GPR : RegisterClass<"ABC", [v1i16, v1f16], 16, (add


&nbsp; &nbsp; IA, IB, IC, ID, IE, IF, IG, IH


&nbsp; )&gt;;



&nbsp;


def MGPR : RegisterClass<"ABC", [v1i16, v1f16], 16, (add


&nbsp; &nbsp; IA, IB, IC, ID, IE, IF, IG, IH


&nbsp; )&gt;;



&nbsp;


def SGPR32 : RegisterClass<"ABC", [ i32, f32 ], 32, (add


&nbsp; &nbsp; DS0, DS1, DS2, DS3, DS4, DS5, DS6, DS7, DS8, DS9,
DS10,DS11,


&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
&nbsp; &nbsp; DS12, DS13, DS14, DS15


&nbsp; )&gt;;



&nbsp;


def uimm2 : Operand<i32&gt;, ImmLeaf<i32, [{return
isUInt<2&gt;(Imm);}]&gt; {


&nbsp; let ParserMatchClass = UImmAsmOperand<2&gt;;


&nbsp; let DecoderMethod = "decodeUImmOperand<2&gt;";


}



&nbsp;


possible type contradiction in the pattern below (use -print-records with
llvm-tblgen to see all expanded records).


vtInt: &nbsp; (vt:{ *:[Other] })


UNREACHABLE executed at
/home/nancy/rpp_llvm/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!



&nbsp;


def LOADbos { // Instruction ABCInst ABCInstMMEMrr


&nbsp; field bits<32&gt; Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0},
index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4},
roffset{4}, roffset{3}, roffset{2}, roffset{1},  roffset{0}, 0, 0, 0, 0, 0, 0,
0, 0, 0 };


&nbsp; field bits<32&gt; SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };


&nbsp; string Namespace = "ABC";


&nbsp; dag OutOperandList = (outs GPR:$rs1);


&nbsp; dag InOperandList = (ins SGPR32:$rbase, MGPR:$roffset,
uimm2:$rshift);


&nbsp; string AsmString = "LOAD&nbsp;&nbsp;&nbsp;&nbsp;
&nbsp; &nbsp; [$rbase + ( $roffset << $rshift )], $rs1";


&nbsp; list<dag&gt; Pattern = [(set v1i16:$rs1, (load (add (v1i32
(bitconvert i32:$rbase)), (shl (v1i32 (sext v1i16:$roffset)), (v1i32
(build_vector uimm2:$rshift))))))];


&nbsp; list<Register&gt; Uses = [];


&nbsp; list<Register&gt; Defs = [];


&nbsp; list<Predicate&gt; Predicates = [];



&nbsp;


&nbsp;


-gen-dag-isel -debug


PATTERN: (ld:{ *:[v1i16] } (add:{ *:[v1i32] } (shl:{ *:[v1i32] } (sext:{
*:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{
*:[i32] })<<P:Predicate_uimm2&gt;&gt;:$rshift)),  (bitconvert:{
*:[v1i32] } i32:{ *:[i32]
}:$rbase)))<<P:Predicate_unindexedload&gt;&gt;<<P:Predicate_load&gt;&gt;


RESULT:&nbsp; (LOADbos:{ *:[v1i16] } i32:{ *:[i32] }:$rbase, v1i16:{
*:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift)


PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } v1i32:{ *:[v1i32]
}:$roffset, (bitconvert:{ *:[v1i32] } i32:{ *:[i32]
}:$rbase)))<<P:Predicate_unindexedstore&gt;&gt;<<P:Predicate_store&gt;&gt;


RESULT:&nbsp; (STORErr v1i16:{ *:[v1i16] }:$rs1, i32:{ *:[i32] }:$rbase,
v1i32:{ *:[v1i32] }:$roffset)



Type set is empty for each HW mode:


possible type contradiction in the pattern below (use -print-records with
llvm-tblgen to see all expanded records).


vtInt: &nbsp; (vt:{ *:[Other] })


UNREACHABLE executed at
/home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!



&nbsp;


&nbsp;


Any idea to solve this problem?


&nbsp;


&nbsp;
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