[llvm-dev] Tablegen PAT limitation?

Celine via llvm-dev
Wed, 20 Nov 2019 04:07:05 -0000

})<<P:Predicate_uimm2&gt;&gt;:$rshift)), (bitconvert:{ *:[v1i32] }
i32:{ *:[i32]
}:$rbase)))<<P:Predicate_unindexedstore&gt;&gt;<<P:Predicate_store&gt;&gt;
RESULT:&nbsp; (STOREbos v1i16:{ *:[v1i16] }:$rs1, i32:{ *:[i32] }:$rbase,
v1i16:{ *:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift)



DAGIselMatcherGen.cpp: 559
Pattern.getSrcPattern()-&gt;dump();&nbsp;
//&nbsp; list<dag&gt; Pattern = [(store v1i16:$rs1, (add (v1i32
(bitconvert i32:$rbase)), (shl (v1i32 (sext v1i16:$roffset)), (v1i32
(build_vector uimm2:$rshift)))))];


In CodeGenDAGPatterns.cpp: 1443
bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp;const SDNodeInfo &amp;NodeInfo,
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp;TreePattern &amp;TP) const {

.....
N-&gt;dump() ; //&nbsp; (sext:{ *:[v1i32] } v1i16:{ *:[i16] }:$roffset)
Why it become v1i16:{ *:[i16] }:$roffset? Should be (sext:{ *:[v1i32] } v1i16:{
*:[v1i16] }:$roffset) as the Pattern defined.


&nbsp; case SDTCisOpSmallerThanOp: {
&nbsp; &nbsp; unsigned BResNo = 0;
&nbsp; &nbsp; TreePatternNode *BigOperand &nbsp; &nbsp;
&nbsp; getOperandNum(x.SDTCisOpSmallerThanOp_Info.BigOperandNum, N,
NodeInfo,
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; BResNo);


NodeToApply-&gt;dump(); //v1i16:{ *:[i16] }:$roffset
BigOperand-&gt;dump();&nbsp; //(sext:{ *:[v1i32] } v1i16:{ *:[i16]
}:$roffset)



&nbsp; &nbsp; return
TI.EnforceSmallerThan(NodeToApply-&gt;getExtType(ResNo),
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp;BigOperand-&gt;getExtType(BResNo));
&nbsp; }





bool TypeInfer::EnforceSmallerThan(TypeSetByHwMode &amp;Small,
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp; &nbsp; &nbsp;TypeSetByHwMode &amp;Big) {

Small-&gt;dump(); //{ *:[i16] }
Big-&gt;dump(); //&nbsp;{ *:[v1i32] }
....
&nbsp; &nbsp; if (none_of(S, isVector) || none_of(B, isVector)) {
&nbsp; &nbsp; &nbsp; Changed |= berase_if(S, isVector) |
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;
&nbsp; &nbsp;berase_if(B, isVector);
&nbsp; &nbsp; }

Changed turn to True here which trigger the final error assert.


How to understand Pattern Match process? Any document?


------------------&nbsp;Original&nbsp;------------------
From:&nbsp;"Krzysztof Parzyszek"<kparzysz at
quicinc.com&gt;;
Date:&nbsp;Tue, Nov 19, 2019 10:09 PM
To:&nbsp;"Celine"<595602881 at qq.com&gt;;"llvm-dev at
lists.llvm.org"<llvm-dev at lists.llvm.org&gt;;

Subject:&nbsp;RE: [llvm-dev]  Tablegen PAT limitation?




Hi,

The problem is with a pattern that has a vt in it: the “vtInt …” printed below
the error message.&nbsp; Could you run llvm-tblgen from a debugger and show
the stack trace from where the error occurred?

&nbsp;

--

Krzysztof Parzyszek  kparzysz at quicinc.com&nbsp;&nbsp; AI tools
development

&nbsp;

From: llvm-dev <llvm-dev-bounces at lists.llvm.org&gt; On Behalf Of
Celine via llvm-dev
 Sent: Tuesday, November 19, 2019 6:52 AM
 To: llvm-dev <llvm-dev at lists.llvm.org&gt;
 Subject: [EXT] [llvm-dev] Tablegen PAT limitation?



&nbsp;

Hello,


&nbsp;


def GPR : RegisterClass<"ABC", [v1i16, v1f16], 16, (add


&nbsp; &nbsp; IA, IB, IC, ID, IE, IF, IG, IH


&nbsp; )&gt;;



&nbsp;


def MGPR : RegisterClass<"ABC", [v1i16, v1f16], 16, (add


&nbsp; &nbsp; IA, IB, IC, ID, IE, IF, IG, IH


&nbsp; )&gt;;



&nbsp;


def SGPR32 : RegisterClass<"ABC", [ i32, f32 ], 32, (add


&nbsp; &nbsp; DS0, DS1, DS2, DS3, DS4, DS5, DS6, DS7, DS8, DS9,
DS10,DS11,


&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
&nbsp; DS12, DS13, DS14, DS15


&nbsp; )&gt;;



&nbsp;


def uimm2 : Operand<i32&gt;, ImmLeaf<i32, [{return
isUInt<2&gt;(Imm);}]&gt; {


&nbsp; let ParserMatchClass = UImmAsmOperand<2&gt;;


&nbsp; let DecoderMethod = "decodeUImmOperand<2&gt;";


}



&nbsp;


possible type contradiction in the pattern below (use -print-records with
llvm-tblgen to see all expanded records).


vtInt: &nbsp; (vt:{ *:[Other] })


UNREACHABLE executed at
/home/nancy/rpp_llvm/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!



&nbsp;


def LOADbos { // Instruction ABCInst ABCInstMMEMrr


&nbsp; field bits<32&gt; Inst = { 0, 0, 0, 0, rs1{2}, rs1{1}, rs1{0},
index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4},
roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0,
0, 0 };


&nbsp; field bits<32&gt; SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };


&nbsp; string Namespace = "ABC";


&nbsp; dag OutOperandList = (outs GPR:$rs1);


&nbsp; dag InOperandList = (ins SGPR32:$rbase, MGPR:$roffset,
uimm2:$rshift);


&nbsp; string AsmString =
"LOAD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
&nbsp; [$rbase + ( $roffset << $rshift )], $rs1";


&nbsp; list<dag&gt; Pattern = [(set v1i16:$rs1, (load (add (v1i32
(bitconvert i32:$rbase)), (shl (v1i32 (sext v1i16:$roffset)), (v1i32
(build_vector uimm2:$rshift))))))];


&nbsp; list<Register&gt; Uses = [];


&nbsp; list<Register&gt; Defs = [];


&nbsp; list<Predicate&gt; Predicates = [];



&nbsp;


&nbsp;


-gen-dag-isel -debug


PATTERN: (ld:{ *:[v1i16] } (add:{ *:[v1i32] } (shl:{ *:[v1i32] } (sext:{
*:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{
*:[i32] })<<P:Predicate_uimm2&gt;&gt;:$rshift)), (bitconvert:{
*:[v1i32] } i32:{ *:[i32]
}:$rbase)))<<P:Predicate_unindexedload&gt;&gt;<<P:Predicate_load&gt;&gt;


RESULT:&nbsp; (LOADbos:{ *:[v1i16] } i32:{ *:[i32] }:$rbase, v1i16:{
*:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift)


PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } v1i32:{ *:[v1i32]
}:$roffset, (bitconvert:{ *:[v1i32] } i32:{ *:[i32]
}:$rbase)))<<P:Predicate_unindexedstore&gt;&gt;<<P:Predicate_store&gt;&gt;


RESULT:&nbsp; (STORErr v1i16:{ *:[v1i16] }:$rs1, i32:{ *:[i32] }:$rbase,
v1i32:{ *:[v1i32] }:$roffset)



Type set is empty for each HW mode:


possible type contradiction in the pattern below (use -print-records with
llvm-tblgen to see all expanded records).


vtInt: &nbsp; (vt:{ *:[Other] })


UNREACHABLE executed at
/home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!



&nbsp;


&nbsp;


Any idea to solve this problem?


&nbsp;


&nbsp;
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