[llvm-dev] Operand equality constraint in TableGen

Manjunath Kudlur via llvm-dev
Mon, 08 Apr 2019 22:45:15 -0000

Hello,

https://reviews.llvm.org/D53815 introduced extra checks in TableGen for the
TIED_TO constraint between MC operands. One of the check ensures that one
of the operands is a def and the other is a use. In the backend I am
implementing, there are instructions that have the encoding constraint that
two source operands need to be the same register numbers, but coming from
two different register files. The following snippet used to work correctly
before:

class EqConstraint {
  string Constraints ="$op0 = $a";
}

multiclass Inst<bits<5> opc, RegType rt, string opcode> {
  defm "" : InstS2D1<opc, (outs), (ins REGFILE0:$op0, REGFILE1:$a,
rt:$op1),
                       asmStr#"\t[$op0], [$a], $op1">
          , EqConstraint ;
}

but fails after rebasing on top of release_80. How can I enforce equality
constraints between two source operands? I will greatly appreciate any help.

Thanks,
Manjunath
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