[llvm-dev] [EXT] Please expose predicates to MachineVerifier

Eli Friedman via llvm-dev
2019-04-01T18:33:26Z

There's already an existing hook for adding target-specific verification
logic in the target's TargetInstrInfo::verifyInstruction.  That doesn't
really scale to checking that you're using an appropriate subtarget for
every instruction, though.  (You could, but it would involve a lot of redundant
hand-written code for many targets.)

We can't really use any of the existing code generated by TableGen to
perform the checks in question; I don't think we currently expose the
relevant predicates in any useful way.  But it would probably be appropriate to
extend TableGen to generate code for those checks, I think.  It would probably
also require some modifications to the TableGen files themselves; currently, at
least for some targets, we use Requires predicates on instructions which are
legal, but we don't want the TableGen'ed isel to select for some reason.

-Eli

From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Mark
Schimmel via llvm-dev
Sent: Monday, April 1, 2019 11:21 AM
To: llvm-dev at lists.llvm.org
Subject: [EXT] [llvm-dev] Please expose predicates to MachineVerifier

Could we expose predicates defined in the target InstrInfo.td file to the
MachineVerifier? We use BuildMI() to create many instructions after ISEL, but
the predicates are not being checked at this point. Thus, I could forget to
check the target and build an instruction that is illegal for a specific
configuration. In such a case it would be nice if the MachineVerifier could
detect this for me.

Example predicate IsCore8 usage:

def ADDx: BINOP<...>, Requires<[IsCore8]>;

let Predicates=[IsCore8] in {
def : SUBX: BINOP<...>;
}

The predicates are encoded into the targets GenDAGIsel file but not anywhere
else that I can find:
  OPC_CheckPatternPredicate, 4, // (Subtarget.isCore8())

Thanks

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