[llvm-dev] Unmodeled side effects and scheduling latency

Mattias Eriksson V via llvm-dev
Mon, 24 Sep 2018 16:22:30 -0000

Hi!

I Have a question on how to think about instructions marked with
"hasSideEffects = 1" in the scheduler. In my out-of-tree back-end we
recently had this situation:

SU(0): set_configuration_reg
SU(1): read_from_memory

SU(0) is marked with "hasSideEffects = 1".
ScheduleDAGInstrs::buildSchedGraph() considered there to be an
order-dependency between the instructions, but set its latency to 0. So
our custom VLIW scheduler put SU(0) and SU(1) in the same bundle. In
reality the configuration register actually affects how the read
behaves, so bundling these two caused a bug.

Is the scheduler correct in setting the latency to 0 correct in this case?


Mattias