[llvm-dev] Stuck with instruction in tablegen

Michael Stellmann via llvm-dev
Tue, 10 Jul 2018 08:14:18 -0000

Yes, the "F" register equals to X86's "EFLAGS" register,
and indeed, the Z80 treats AF (i.e. the 8 bit accumulator and the 8 bit flags)
as a 16-bit pair, just like HL, being composed of the registers H and L - and in
fact, in the original Z80RegisterInfo.td, A and F are aliased to the pair AF,
just like HL.

If I understood you correctly, you are proposing changing

  [(set A, F, ...

to

  [(set AF, ...

This would affect the SDTypeProfile from

def SDTBinOpRF  : SDTypeProfile<2, 2, [SDTCisInt<0>,
                                       SDTCisFlag<1>,
                                       SDTCisSameAs<2, 0>,
                                       SDTCisSameAs<3, 0>]>;

i.e. a (8-bit) integer register "A", and a (8-bit) flag register
"F" to merge into a (16-bit) integer register "AF"

def SDTBinOpRF  : SDTypeProfile<1, 2, [SDTCisInt<0>,
                                       SDTCisSameAs<1, 0>,
                                       SDTCisSameAs<2, 0>]>;

which would omit the "SDTCisFlag".

I'm not that much into LLVM yet (started with that only ~1 week ago) but I
would expect that this would have to be dealt with somewhere else in the code,
right?

Michael