[llvm-dev] When AVR backend generates mulsu instruction ?

vivek pandya via llvm-dev
Sun, 26 Feb 2017 11:41:59 -0000

Hello LLVMDevs,

I am looking for an example for how to lower LLVM IR to mulsu kind of
instruction.  I found that AVR back end have such instruction but
AVRInstrInfo.td does not define any DAG pattern for which this
instruction gets emitted.
def MULSURdRr : FMUL2RdRr<1,
(outs),
(ins GPR8:$lhs, GPR8:$rhs),
"mulsu\t$lhs, $rhs",
[]>,
Requires<[SupportsMultiplication]>;
 Also simple grep around related words does not show any other information.

Can some one explain me how this kind of instruction should be lowered ?

Sincerely,
Vivek
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