[llvm-dev] MC PowerPC 32 bit vs. 64 bit

Hal Finkel via llvm-dev
Mon, 07 Nov 2016 17:31:47 -0000

Hi Keve,

As you've noticed, this is not modeled currently: We should, at least in
theory, be selecting the 64-bit instructions with their associated registers
when in 64-bit mode. Because the assembly is ambiguous in this regard, this does
not matter for the purpose of printing the resulting assembly code (it will look
the same regardless) nor will it matter for the purpose of reassembling the
instructions. This will likely be confusing it you're trying to do analysis
on the disassembled instructions, and I'd be happy to review a patch that
improves our handling here.

 -Hal

----- Original Message -----
> From: "Keve via llvm-dev" <llvm-dev at lists.llvm.org>
> To: llvm-dev at lists.llvm.org
> Sent: Sunday, November 6, 2016 1:24:22 PM
> Subject: [llvm-dev] MC PowerPC 32 bit vs. 64 bit
>
> Hi,
> over the past days I have been proofing a concept involving LLVM MC
> on
> the PowerPC target. The 32 bit part went quite ok, but i am puzzled
> with
> the results I get using the 64 bit target.
> When disassembling in 64bit some instructions refer to GPRs in
> PPC::R0
> to PPC::R31, some refer to PPC::X0 to PPC::X31.
> I understand that the registers are modeled with Rx referring to the
> 32bit parts and Xx referring to the 64bit parts, but the way it looks
> to
> me right now is that you only get the 64bit registers if the opcode
> is
> available exclusively in 64bit mode.
> I have seen that many instructions have been duplicated to support 32
> bit registers and 64 bit register, e.g. oris vs. oris8, but the
> disassembler does not pick the 64 bit variant.
> PPCGenDisassemblerTables.inc does not have anything about oris8, only
> oris.
> As a user of the Disassembler I would expect it to return me the
> 64bit
> instruction referencing the 64bit registers if I ask it to
> disassemble a
> ppc64 target.
>
> Is this intended behavior or am I just missing some bit somewhere?
> Thank you very much in advance for clarifying this.
>
> Cheers,
>
> Keve
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>

--
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory