[llvm-dev] Generate Register Indirect mode instruction

Alex Bradley via llvm-dev
Mon, 17 Oct 2016 21:45:12 -0000

Gentle Ping !!

I would appreciate any help on this. I want to generate following as
described by Krzysztof :

%v1 = load i32, i32* %a
%v2 = load i32, i32* %b
%v3 = add i32 %v1, %v2
store i32 %v3, i32* %c

maps to (using invented mnemonics):

ASSIGN R0, %a
ASSIGN R1, %b
ASSIGN R2, %c
ADD *R2, *R0, *R1

Thanks.

Regards,
Alex

On 14 Oct 2016 1:00 p.m., "Alex Bradley" <alexbradley.bqc at
gmail.com> wrote:

>
> > If I understand correctly:
> >
> > %v1 = load i32, i32* %a
> > %v2 = load i32, i32* %b
> > %v3 = add i32 %v1, %v2
> > store i32 %v3, i32* %c
> >
> > maps to (using invented mnemonics):
> >
> > ASSIGN R0, %a
> > ASSIGN R1, %b
> > ASSIGN R2, %c
> > ADD *R2, *R0, *R1
> >
> > I.e. pattern
> >   (store %c, (add (load %a), (load %b)))
> > becomes
> >   (ADD (ASSIGN R2, %c), (ASSIGN R0, %a), (ASSIGN R1, %b))
> >
>
> Yes. Exactly.
>
> Regards,
> Alex
>
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