[llvm-dev] Specifying DAG patterns in the instruction

Rail Shafigulin via llvm-dev
Fri, 29 Jan 2016 19:39:58 -0000

On Thu, Jan 28, 2016 at 8:34 PM, Dylan McKay <dylanmckay34 at gmail.com>
wrote:

> Try visualising the DAG like this.
>
> ```
>                        ---- GPR:$rA
>                       /
> set GPR:$rd  ---- add
>                       \
>                        ---- GPR:$rB
> ```
>
> Each instruction forms a DAG with its operands being subnodes.
>
> The core instruction selection logic just looks for the pattern `(set
> GPR:$rd, (add GPR:$rA, GPR:$rB))`. It then becomes a simple substitution.
> This is a DAG because there all nodes are directed and acyclic.
>


Am I correct in my understanding that each node can either be a register or
of type SDNode defined in TargetSelectionDAG.td?


> On Thu, Jan 28, 2016 at 7:33 PM, Rail Shafigulin via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
>
>> I'm confused about how to specify DAG patterns for a given
instruction
>>
>> Here is an example for my target
>>
>> class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode>
>>   : ALU_RR<subOp, asmstr,
>>            [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>;
>>
>> def ADD  : ALU1_RR<0x0, "l.add", add>;
>>
>> The set operation simply creates a list. The add operation creates a
>> union. So at the end  [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32
>> GPR:$rB)))] becomes a just a regular set. How come this is a DAG? I
feel
>> like I'm missing something. Would anyone be able to help with the
>> explanation?
>>
>> --
>> Rail Shafigulin
>> Software Engineer
>> Esencia Technologies
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> llvm-dev at lists.llvm.org
>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>>
>>
>


--
Rail Shafigulin
Software Engineer
Esencia Technologies
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