[LLVMdev] Memory alignment model on AVX, AVX2 and AVX-512 targets

Chandler Carruth
2014-12-14T22:26:43Z

FWIW, this makes sense to me. I'd be interested to hear from folks that are
supporting AMD processors which do support AVX to ensure that there isn't
an undue runtime penalty for these.

On Sun, Dec 14, 2014 at 7:08 AM, Demikhovsky, Elena <
elena.demikhovsky at intel.com> wrote:
>
>  Hi,
>
> I think that
> def FeatureVectorUAMem :
SubtargetFeature<"vector-unaligned-mem",
>                                           "HasVectorUAMem",
"true",
>                  "Allow unaligned memory operands on vector/SIMD
> instructions">;
>
> should be switched-ON on AVX and AVX-512 instructions because:
>
> According to the AVX spec:
> “Most arithmetic and data processing instructions encoded using the VEX
> prefix and
> performing memory accesses have more flexible memory alignment requirements
> than instructions that are encoded without the VEX prefix. Specifically,
> • With the exception of explicitly aligned 16 or 32 byte SIMD load/store
> instructions,
> most VEX-encoded, arithmetic and data processing instructions operate in
> a flexible environment regarding memory address alignment, i.e. VEX-encoded
> instruction with 32-byte or 16-byte load semantics will support unaligned
> load
> operation by default. Memory arguments for most instructions with VEX
> prefix
> operate normally without causing #GP(0) on any byte-granularity alignment
> (unlike Legacy SSE instructions).”
>
> And the same for AVX-512.
>
> We do not require any alignment while folding loads on the “Peephole
> Optimizations” on these targets.
>
>
>
>
>     - * Elena*
>
>
>
>
>
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