[LLVMdev] Memory alignment model on AVX, AVX2 and AVX-512 targets

Demikhovsky, Elena
2014-12-14T15:08:16Z

Hi,

I think that
def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
                                          "HasVectorUAMem",
"true",
                 "Allow unaligned memory operands on vector/SIMD
instructions">;

should be switched-ON on AVX and AVX-512 instructions because:

According to the AVX spec:
"Most arithmetic and data processing instructions encoded using the VEX
prefix and
performing memory accesses have more flexible memory alignment requirements
than instructions that are encoded without the VEX prefix. Specifically,
* With the exception of explicitly aligned 16 or 32 byte SIMD load/store
instructions,
most VEX-encoded, arithmetic and data processing instructions operate in
a flexible environment regarding memory address alignment, i.e. VEX-encoded
instruction with 32-byte or 16-byte load semantics will support unaligned load
operation by default. Memory arguments for most instructions with VEX prefix
operate normally without causing #GP(0) on any byte-granularity alignment
(unlike Legacy SSE instructions)."

And the same for AVX-512.

We do not require any alignment while folding loads on the "Peephole
Optimizations" on these targets.



-        Elena



---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20141214/8a01dde7/attachment.html>