[LLVMdev] Virtual register def doesn't dominate all uses

Quentin Colombet
Fri, 24 Oct 2014 17:27:07 -0000

Hi Boris,

I don’t see any phis in your machine code whereas the IR had some. This means
you are already pretty late in the pipeline of the backend (i.e., after SSA form
has been deconstructed).
Do you have any custom pass between instruction selection and the PHIElimination
pass?

If so, I would look into them.

Cheers,
-Quentin

> On Oct 24, 2014, at 7:53 AM, Boris Boesler <baembel at gmx.de> wrote:
>
> Hi!
>
> During my backend development I get the error message for some tests:
> *** Bad machine code: Virtual register def doesn't dominate all uses.
***
>
> (C source-code, byte-code disassembly and printed machine code at the end
of the email)
>
> The first USE of vreg4 in BB#1 has no previous DEF in BB#0 or #1. But why?
I can't see how the LLVM byte-code is transformed to the lower machine code.
>
> One possible reason could be that I haven't implemented all operations,
eg I didn't implement MUL at this stage. Their "state" is LEGAL
and not CUSTOM or EXPAND. But it fails with implemented operations as well.
>
> What did I do wrong? Missing implementation for some operations? What did I
miss to implement?
>
> Thanks in advance,
> Boris
>
> ----8<----
>
> C source-code:
> int simple_loop(int end_loop_index)
> {
>  int sum = 0;
>  for(int i = 0; i < end_loop_index; i++) {
>    sum += i;
>  }
>  return(sum);
> }
>
>
> LLVm byte-code disassembly:
> ; Function Attrs: nounwind readnone
> define i32 @simple_loop(i32 %end_loop_index) #1 {
> entry:
>  %cmp4 = icmp sgt i32 %end_loop_index, 0
>  br i1 %cmp4, label %for.cond.for.end_crit_edge, label %for.end
>
> for.cond.for.end_crit_edge:                       ; preds = %entry
>  %0 = add i32 %end_loop_index, -2
>  %1 = add i32 %end_loop_index, -1
>  %2 = zext i32 %0 to i33
>  %3 = zext i32 %1 to i33
>  %4 = mul i33 %3, %2
>  %5 = lshr i33 %4, 1
>  %6 = trunc i33 %5 to i32
>  %7 = add i32 %6, %end_loop_index
>  %8 = add i32 %7, -1
>  br label %for.end
>
> for.end:                                          ; preds =
%for.cond.for.end_crit_edge, %entry
>  %sum.0.lcssa = phi i32 [ %8, %for.cond.for.end_crit_edge ], [ 0, %entry ]
>  ret i32 %sum.0.lcssa
> }
>
>
> The emitted blocks are:
> Function Live Ins: %R0 in %vreg2
>
> BB#0: derived from LLVM BB %entry
>    Live Ins: %R0
> 	%vreg2<def> = COPY %R0; IntRegs:%vreg2
> 	%vreg3<def> = MV 0; SRegs:%vreg3
> 	CMP %vreg2, 1, %FLAG<imp-def>; IntRegs:%vreg2
> 	%vreg6<def> = COPY %vreg3; SRegs:%vreg6,%vreg3
> 	BR_cc <BB#2>, 20, %FLAG<imp-use,kill>
> 	BR <BB#1>
>    Successors according to CFG: BB#1(20) BB#2(12)
>
> BB#1: derived from LLVM BB %for.cond.for.end_crit_edge
>    Predecessors according to CFG: BB#0
> 	%vreg4<def> = MV %vreg4; IntRegs:%vreg4
> 	%vreg5<def> = ADD %vreg4<kill>, -1; IntRegs:%vreg5,%vreg4
> 	%vreg0<def> = COPY %vreg5<kill>; SRegs:%vreg0 IntRegs:%vreg5
> 	%vreg6<def> = COPY %vreg0; SRegs:%vreg6,%vreg0
>    Successors according to CFG: BB#2
>
> BB#2: derived from LLVM BB %for.end
>    Predecessors according to CFG: BB#0 BB#1
> 	%vreg1<def> = COPY %vreg6<kill>; SRegs:%vreg1,%vreg6
> 	%R0<def> = COPY %vreg1; SRegs:%vreg1
> 	RETURN %R0<imp-use>
>
> # End machine code for function simple_loop.
>
> *** Bad machine code: Virtual register def doesn't dominate all uses.
***
> - function:    simple_loop
> - basic block: BB#1 for.cond.for.end_crit_edge (0x7fd7cb025250)
> - instruction: %vreg4<def> = MV %vreg4; IntRegs:%vreg4
> LLVM ERROR: Found 1 machine code errors.
>
>
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