[LLVMdev] predicates vs. requirements [TableGen, X86InstrInfo.td]

Tom Stellard
Fri, 19 Sep 2014 00:35:44 -0000

On Thu, Sep 18, 2014 at 03:25:07PM -0600, Sanjay Patel
wrote:
> I tried to add an 'OptForSize' requirement to a pattern in
X86InstrSSE.td,
> but it appears to be ignored. However, the condition was detected when
> specified as a predicate.
>
> So this doesn't work:
>    def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))), (VMOVDDUPrm
addr:
> $src)>,
>                  *Requires<[OptForSize**]>*;
>
> But this does:
> *   let Predicates = [OptForSize] in* {
>      def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))), (VMOVDDUPrm
addr
> :$src)>;
>    }
>
> I see both forms used on some patterns like this:
> *  let Predicates = [HasAVX] *in {
>     def : Pat<(X86Movddup (loadv2f64 addr:$src)),
>               (VMOVDDUPrm addr:$src)>, *Requires<[HasAVX]>*;
>   }
>
> Is a predicate different than a requirement or is this a bug?
>
> There are existing patterns that specify 'OptForSize' with
"Requires", but
> they are not behaving as I expected.
>
> Example:
>   // For scalar unary operations, fold a load into the operation
>   // only in OptForSize mode. It eliminates an instruction, but it also
>   // eliminates a whole-register clobber (the load), so it introduces a
>   // partial register update condition.
>   def : Pat<(f32 (fsqrt (load addr:$src))),
>             (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
>             Requires<[HasAVX, OptForSize]>;
>
> This is generated:
>     vsqrtss    (%rdi), %xmm0, %xmm0
>
> regardless of whether I specify -Os or -O1 with clang.

You might want to take a look at the Mips target, it has a
class called PredicateControl defined in Mips.td, which
handles merging predicates together into a single list.

Maybe you could do something similar for x86.

-Tom

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