[LLVMdev] Is shortening a load a bug?

Bagel
Thu, 11 Sep 2014 22:03:29 -0000

When the IR specifies a 32 bit load can it be changed to a narrower load?
What if the load is from memory (e.g. a peripheral) that only supports 32-bit
access?
Consider the following IR:
----
target datalayout =
"e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32"
target triple = "thumbv7m-unknown-unknown"
@f = external global i32
define zeroext i8 @bar() nounwind {
L.0:
	%rv.0 = alloca i8
	%0 = load i32* @f
	%1 = trunc i32 %0 to i8
	ret i8 %1
}
----
Which for the arm cortex-m3 generates:
----
bar:
	movw	r0, :lower16:f
	movt	r0, :upper16:f
	ldrb	r0, [r0]
	bx	lr
----
Although we are only interested in low 8-bits, the load MUST be a 32-bit load.

Using a "load volatile" fixes this, but this is overkill as the memory
location
is not volatile.

Am I missing something, or is this a bug?

brian