[LLVMdev] Partial instruction match in the backend

Sam Parker
Sat, 10 May 2014 13:36:52 -0000

Hi,
You're probably going to want to create your own node and then do some
custom lowering in your TargetLowering class. Then you can use DAG to DAG. Check
out the ARM and x86 backends for plenty of examples.

Good luck,
Sam

Sam Parker
Research Student
Electronic Systems Design Group
School of Electronic, Electrical and Systems Engineering
Loughborough University

----- Reply message -----
From: "deadal nix" <deadalnix at gmail.com>
To: <llvmdev at cs.uiuc.edu>
Subject: [LLVMdev] Partial instruction match in the backend
Date: Sat, May 10, 2014 02:12

Hi,

I'm trying to generate DAG to DAG with several instructions that are
variadic in their input and output.

As far as I can tell, tablegen do not provide anything for me to match these
variadic outputs. However, it can match the input quite nicely.



My initial idea was to call Select to let tablegen match the node, and then fix
the outs of the matched instruction. However, it look like tablegen generated
matching code try to substitute the old node with the matched one immediately,
which result in error as the node do not have the right outputs. Is there a way
to say to tablegen "hey, match this node, but don't substitute, I have
extra work to do", and if not, how difficult would it be to create one ?
Can someone give me some pointers ?



The second approach I've tried is to match completely with custom code. This
seems like a lot of unnecessary work, and if matching constants arguments and
alike is simple, I'm not sure what i'm supposed to do when argument are
themselves can be the result of any kind of computation that must be matched ?
What would be the code match a add manually for instance ? Is there something I
can look at in some backend ?



Thank by advance for any help you can provide.
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