[LLVMdev] Add support for ldr pseudo instruction in ARM integrated assembler

David Peixotto
Fri, 25 Oct 2013 17:33:23 -0000

Both armasm and gnu as support an ldr pseudo instruction for loading
constants that lowers to either a mov, movn, or a pc-relative ldr from the
constant pool. It would be great if the llvm integrated assembler could
support this feature as well.

For example, using gnu as to compile this code:
    .text
    foo:
      ldr r0, =0x1
      ldr r0, =-0x1
      ldr r0, =0x1000001
      ldr r0, =bar
      ldr r0, =baz
    bar:

Produces an object file like this (with relocations shown):
    Disassembly of section .text:
      00000000 <foo>:
         0:   e3a00001        mov     r0, #1
         4:   e3e00000        mvn     r0, #0
         8:   e59f0004        ldr     r0, [pc, #4]    ; 14 <bar>
         c:   e59f0004        ldr     r0, [pc, #4]    ; 18 <bar+0x4>
        10:   e59f0004        ldr     r0, [pc, #4]    ; 1c <bar+0x8>

      00000014 <bar>:
        14:   01000001        .word   0x01000001
        18:   00000014        .word   0x00000014
                              18: R_ARM_ABS32 .text
        1c:   00000000        .word   0x00000000
                              1c: R_ARM_ABS32 baz

Currently the llvm integrated assembler fails on this input with an error
like:
    error: unexpected token in operand
      ldr r0, =0x1
              ^
I am interested in seeing support for this feature added to the integrated
assembler. Is anybody planning to add this feature? I am willing to do the
work, but I am not sure exactly where to start so I thought I would bring it
up here in case anybody has some suggestions (or wants to implement it
themselves :)

CC'ing some recent contributors to the llvm arm assembler.

gnu as reference:
https://sourceware.org/binutils/docs/as/ARM-Opcodes.html#ARM-Opcodes

-David

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