[LLVMdev] Instructions working on 64bit registers without true support for 64bit operations

Tom Stellard
Thu, 12 Jul 2012 13:08:24 -0000

On Thu, Jul 12, 2012 at 01:22:39PM +0200, Fabian Scheler
wrote:
> Hi Micah,
>
> >  We have a very similar setup with the AMDIL backend(some operations
support 64bit some don't).
> >
> > What we do is we enable MVT::i64, set legal to all operands that are
legal and then set everything else to expand.
>
> thanks for your hint. Unfortunately, I didn't find any time to work on
> my problem in the meantime as I was busy preparing lectures. However,
> the summer term is almost over now and I can get back to this.
>
> I already tried what you suggested, however I still end up getting the
> following error message:
>
> LLVM ERROR: Cannot select: 0x2299fb0: i64 = Constant<1> [ORD=1]
[ID=1]
>
> Just setting the Action to Expand here via
>
>  setOperationAction(ISD::Constant,MVT::i64,Expand);
>
> does not solve the problem. I took a look into your AMDIL-patch and
> found out that your target supports this operation. I have the feeling
> that this has to be lowered manually or has to be handled by
> ISelDAGtoDAG or similar.
>
> Well, I guess I have to dig a little bit deeper. If you have any other
> suggestion - I definitely am interested ;-)
>

I took a look at lib/CodeGen/SelectionDAG/LegalizeDAG.cpp and it
doesn't look like there is an Expand operation implemented for
ISD::Constant.  I think you'll either need implement Expand for
ISD::Constant or Custom lower it in your backend.

Also, why is your frontend generating 64-bit constants?


-Tom
> Ciao, Fabian
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