[LLVMdev] Instructions working on 64bit registers without true support for 64bit operations

Fabian Scheler
Thu, 12 Jul 2012 11:22:39 -0000

Hi Micah,

>  We have a very similar setup with the AMDIL backend(some operations
support 64bit some don't).
>
> What we do is we enable MVT::i64, set legal to all operands that are legal
and then set everything else to expand.

thanks for your hint. Unfortunately, I didn't find any time to work on
my problem in the meantime as I was busy preparing lectures. However,
the summer term is almost over now and I can get back to this.

I already tried what you suggested, however I still end up getting the
following error message:

LLVM ERROR: Cannot select: 0x2299fb0: i64 = Constant<1> [ORD=1] [ID=1]

Just setting the Action to Expand here via

 setOperationAction(ISD::Constant,MVT::i64,Expand);

does not solve the problem. I took a look into your AMDIL-patch and
found out that your target supports this operation. I have the feeling
that this has to be lowered manually or has to be handled by
ISelDAGtoDAG or similar.

Well, I guess I have to dig a little bit deeper. If you have any other
suggestion - I definitely am interested ;-)

Ciao, Fabian