[LLVMdev] Custom lowering binary operations on one register machines.

Evan Cheng
Tue, 11 Nov 2008 16:43:03 -0000

On Nov 10, 2008, at 9:51 AM, sanjiv gupta wrote:

> Ours is an accumulator based architecture.
>
> So one operand of ADD/SUB operations is in REG (accumulator) and the
> other one is in Memory. The result can be left either in REG or
> memory.
>
> The LLVM DAG for such operations expect both operands in REG.
>
> for example:
> char a, b, c, d, e;
> a = (b - c) + (d - e);
>
> generates
>
> addc:i8 (subc:i8(b,c), subc:i8(d,e))
>
> Looks like we need to custom lower addc here.  LegalizeOp needs
> modification to allow custom lowering of ADDC, etc.I will post a patch
> to do the same.
>
> Any suggestions on how do we custom lower such things?
> is using MFI::CreateFixedObject () to generate a FI and then using
> that
> FI to Store one REG operand to memory and then generate a Load from
> that
> FI is a good idea?

That should work. I don't see an alternative. I don't think it's
legal
to re-associate the expression, right?

Evan

>
>
>
> sth like
>
> store (subc:i8(d, e), FI)
> addc:i8(subc:i8(b,c) - load (FI))
>
> - Sanjiv
>
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