[LLVMdev] Custom Lowering and fneg

Eli Friedman
Wed, 10 Sep 2008 23:40:47 -0000

On Wed, Sep 10, 2008 at 4:20 PM, Villmow, Micah <Micah.Villmow at amd.com>
wrote:
>> What I cannot figure out is why it is attempting to pattern match on
> an i32
>> when there are no i32's in my test program.
>
> With the regular SPARC backend, what ends up happening is the following:
> 1. The float is passed in an integer register (here's where the i32
> first shows up)
> 2. The DAG combiner notices this, and combines the
> fneg(bit_convert(arg)) to bit_convert(xor(arg, sign_bit)).
> 3. The store of the bit_convert gets turned into an i32 store, and
> there are now no more floats in the code.
>
> I removed the SPARC pattern matching instructions for the fneg
> instruction because I don't want this behavior.

Hmm?  I'm not sure what code you're talking about... the code I'm
talking about is cross-architecture.  See DAGCombiner::visitFNEG in
lib/CodeGen/SelectionDAG/DAGCombiner.cpp.

>> On another not, is there any known examples of using Tablegen with a
>> typeless register class?
>
> What do you mean?
>
> The register types that are generated themselves don't hold any type
> information. How the bits are treated depends on the instruction being
> generated. My register are 128bit in width that can hold either 32bit
> floats and ints, or 64 bit floats in scalar or vector form.

For this to work, all you have to do is define all your register
classes to use the same set of registers.  See FR32. FR64, and VR128
(floats, doubles, and vectors in SSE registers) in X86RegisterInfo.td
for an example.

-Eli