[LLVMdev] Prevent a intrinsic to be reordered?

Julio
Mon, 15 Sep 2008 07:16:55 -0000

Nothing... I'll show you all the info related to:

The intrinsic:  def int_soru_sre : Intrinsic<[llvm_void_ty, llvm_i32_ty],
[IntrWriteMem]>;

The lower instruction (in MIPS):
class SORUI<bits<6> op, dag outs, dag ins, string asmstr,
list<dag> pattern,
         InstrItinClass itin>: FI<op, outs, ins, asmstr, pattern, itin>
{
  let isBarrier = 1; // or call, hassideefects, ..., nothing work
}

def SORU_SRE: SORUI<0b110011, (outs), (ins uimm16:$imm), "sre
$imm",
               [(int_soru_sre imm:$imm)], IISoru>;

(With IISoru I made all the possible changes: a lot of cycles or none with
all the functional units or none)

And an example:
    tail call void @llvm.soru.sre( i32 5 )
    mul i32 %b, %a        ; <i32>:0 [#uses=1]

is coded as:

    mult $2, $5, $4
    sre 5

Best regards.
Julio

2008/9/14 Anton Korobeynikov <asl at math.spbu.ru>

> Hello, Julio
>
> > These later things are ignored, I don't know if when the intrinsic
is
> > lowered, then it doesn't matter (or perhaps the reorder is made
> > before).
> What is the description of the instruction you're lowering intrinsic
> into? Have you looked for the instruction flags defined in Target.td
> file? You instruction should definitely have "isBarrier" flag
set.
>
> --
> With best regards, Anton Korobeynikov.
>
> Faculty of Mathematics & Mechanics, Saint Petersburg State University.
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20080915/5140bf01/attachment.html>