[LLVMdev] How to partition registers into different RegisterClass?

Tzu-Chien Chiu
Mon, 25 Jul 2005 09:56:28 -0000

2005/7/24, Chris Lattner <sabre at nondot.org>:
> Ah, ok. In that case, you want to put all of the registers in one register
> file, and not make the constant register allocatable (e.g. see
> X86RegisterInfo.td, and note how the register classes include EBP and ESP,
> but do not register allocate them (through the definition of
> allocation_order_end()).
>
> -Chris

Hope I understand you correctly:

def C0 : ConstFpReg<0, "c0">;
...
def C200 : ConstFpReg<199, "c200">;

def I0 : ConstIntReg<0, "i0">;
...
def I100 : ConstIntReg<100, "i100">;

def R0 : TempReg<0, "r0">;
def R32 : TempReg<31, "r32">;

def V0 : InputReg<0, "v0">;
..
def V10 : InputReg<9, "v10">;

def O0 : OutputReg<0, "o0">;
..
def O4 : OutputReg<4, "o4">;

def FloatingPointRC : RegisterClass<packed, 128,
    [R0, R1, R2, ..., R32,
     C0, C1, ..., C200,
     V0, ..., V10,
     O1, O2, O3, O4]> {
  let Methods = [{
    iterator allocation_order_end(MachineFunction &MF) const {
      return end()-(4+10+200); // only TempReg can be allocated
  }];
}

def IntegerRC : RegisterClass<packed, 128,
    [I0, I1, ..., I100]>;


And linearly assigning the read-only registers for each definition of them?