llvm dev - Feb 2014 - [LLVMdev] ifconversion before register allocation

Hi all,

I am using llvm backend to generate binary for a specific accelerator. I
would like to convert instructions into predicated form when instructions
are still in SSA form. It looks like that ifconversion execution flow is
different when instructions are in SSA form. However, I am encountering
many problems (specially with registers) when I use it before register
allocation. I was wondering if anybody could confirm that if-conversion can
be used before register allocation? Any suggestion is really appreciated.

Thanks
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On Feb 12, 2014, at 3:38 PM, mahdi hamzeh <mahdy.hamzeh at gmail.com>
wrote:
> Hi all,
> 
> I am using llvm backend to generate binary for a specific accelerator. I
would like to convert instructions into predicated form when instructions are
still in SSA form. It looks like that ifconversion execution flow is different
when instructions are in SSA form. However, I am encountering many problems
(specially with registers) when I use it before register allocation. I was
wondering if anybody could confirm that if-conversion can be used before
register allocation? Any suggestion is really appreciated.
EarlyIfConverter is the pass designed to run before RA. It is not enabled by
default. It is quite different from the post-ra if-converter. It works on SSA
and does not actually predicate instructions. It generates CMOVs.
—Andy
> 
> Thanks
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

Andy,

I have already enabled EarlyIfConversion but as you said, it does not
predicate instruction (only works for exception safe instructions).

Thanks
Mahdi


On Wed, Feb 12, 2014 at 5:29 PM, Andrew Trick <atrick at apple.com> wrote:
>
> On Feb 12, 2014, at 3:38 PM, mahdi hamzeh <mahdy.hamzeh at gmail.com>
wrote:
>
> > Hi all,
> >
> > I am using llvm backend to generate binary for a specific accelerator.
I
> would like to convert instructions into predicated form when instructions
> are still in SSA form. It looks like that ifconversion execution flow is
> different when instructions are in SSA form. However, I am encountering
> many problems (specially with registers) when I use it before register
> allocation. I was wondering if anybody could confirm that if-conversion can
> be used before register allocation? Any suggestion is really appreciated.
>
> EarlyIfConverter is the pass designed to run before RA. It is not enabled
> by default. It is quite different from the post-ra if-converter. It works
> on SSA and does not actually predicate instructions. It generates CMOVs.
> --Andy
>
> >
> > Thanks
> > _______________________________________________
> > LLVM Developers mailing list
> > LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
>
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