Hi All, I am working to cross compile (just generate assembly code) a simple C code in ARM. First, I use CLANG to get LLVM bytecode, then I use llc to generate assembly for ARM. The problem is it never uses any other register except r0-r3 and always uses spill code even if other register are available to use. Anyone has any idea? Thanks Best Regards, A. Yazdanbakhsh>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>PhD. Student School of Electrical and Computer Engineering University of Wisconsin-Madison E-mail: yazdanbakhsh at wisc.edu <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20121209/b0e48a28/attachment.html>
Hi,> I am working to cross compile (just generate assembly code) a simple C code > in ARM. First, I use CLANG to get LLVM bytecode, then I use llc to generate > assembly for ARM. The problem is it never uses any other register except > r0-r3 and always uses spill code even if other register are available to > use. Anyone has any idea?Some example code and output might be useful. Command line options you're using too. The only thing I can think of is you might not be generating enough register pressure that it *needs* to go beyond r0-r3, and maybe mistaking something else the compiler is doing for a pressure spill. The following function uses r12 for me, for example ("llc -march=arm -o - simple.ll"): @var = global i32 0 define void @foo() { %val1 = load volatile i32* @var %val2 = load volatile i32* @var %val3 = load volatile i32* @var %val4 = load volatile i32* @var store volatile i32 %val1, i32* @var store volatile i32 %val2, i32* @var store volatile i32 %val3, i32* @var store volatile i32 %val4, i32* @var ret void } Tim.
Sound like you are not enabling optimization. Try with -O3. Evan On Dec 9, 2012, at 12:49 AM, Amir Yazdanbakhsh <amir.yazdanbakhsh at gmail.com> wrote:> Hi All, > > I am working to cross compile (just generate assembly code) a simple C code in ARM. First, I use CLANG to get LLVM bytecode, then I use llc to generate assembly for ARM. The problem is it never uses any other register except r0-r3 and always uses spill code even if other register are available to use. Anyone has any idea? > > Thanks > > Best Regards, > A. Yazdanbakhsh > > >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> > > PhD. Student > School of Electrical and Computer Engineering > University of Wisconsin-Madison > E-mail: yazdanbakhsh at wisc.edu > > > <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20121209/d5216edb/attachment.html>
On Sun, Dec 9, 2012 at 7:48 PM, Evan Cheng <evan.cheng at apple.com> wrote:> Sound like you are not enabling optimization. Try with -O3.Ah, of course! I'd forgotten about the extra allocas produced by clang. To expand a little, the spills you're seeing are (probably) specifically created by clang (it creates a shadow variable for each local with alloca). "llc" on its own can't get rid of these, so you'll either want to give clang "-O3" or run the LLVM bitcode through "opt" before "llc". Tim.