similar to: Data is Copying when a new brick is added.

Hello, I have one question about the ALU scheduler. If for example I have one UNIFY volume which is using ALU scheduler with the following config: volume unify type cluster/unify option namespace afr-ns option scheduler rr option scheduler alu # use the ALU scheduler option alu.limits.min-free-disk 3% # Don't create files one a volume with less than 5% free diskspace

5-nodes server and 1 node client are connected by gigabits Ethernet. #] iozone -r 32k -r 512k -s 8G KB reclen write rewrite read reread read write read rewrite read fwrite frewrite fread freread 8388608 32 10559 9792 62435 62260 8388608 512 63012 63409 63409 63138 It seems 32k write/rewrite performance are very

elbert at host1:~$ dpkg -l|grep glusterfs ii glusterfs-client 1.3.8-0pre2 GlusterFS fuse client ii glusterfs-server 1.3.8-0pre2 GlusterFS fuse server ii libglusterfs0 1.3.8-0pre2 GlusterFS libraries and translator modules I have 2 hosts set up to use AFR with

HI all: I met a problem in expending dht volumes, i write in a dht storage directory untile it grew up to 90%,so i add four new volumes into the configur file. But when start again ,the data in directory some disappeared ,Why ??? Was there a special action before expending the volumes? my client cofigure file is this : volume client1 type protocol/client option transport-type

Hi, I just installed and configured a couple of machines with glusterfs (1.4.0-rc3). It seems to work great. Thanks for the amazing software.! I've been looking for something like this for years. I have some feedback and questions. My configuration is a bit complicated. I have two machines each with two disks and each of which with two partitions that I wanted to use (i.e. 8

This fixes a somewhat indeterministic corruption problem on nv17 when there is stuff going on the other fifos (e.g. gallium but I've also reproduced it with an app just SIFM-ing memory around): in some cases it made the blits the X server had scheduled use the wrong pitch. Signed-off-by: Francisco Jerez <currojerez at riseup.net> --- src/nv04_exa.c | 22 ++++++++++++---------- 1

Hi, I have a list of mutations, called "mutList", of the form: > head(mutList) Alu 1 AluJ 2 AluJ/F(R)AM 3 AluJ/FLAM 4 AluJ/FRAM 5 AluJ/monomer 6 AluJb It contains about 500 elements and not all of them contain the sequence "Alu". I tried using this code: Alu<-mutList[which(grep("Alu",mutList)==1)] But that simply returned

From: Peter Arremann <loony at loonybin.org> > Compiles aren't a great benchmark for a box since its 100% cpu and > neglects memory or disk performance but I had the numbers handy > for that :-) BTW, it is 100% ALU and a major strain on the ALU LOAD. In other words, it's not a good benchmark for even CPU. That's why the 3-issue ALU in the Nx586 on-ward blows the

I've been experimenting with llvm/clang as a user for a while now, but now I'm interested in writing my own backend. I'm also developing the target architecture (maybe to go in an fpga eventually) and I'm intentionally making it extremely simple. I think of it as a narrow microcode, because (for example) performing an add requires a sequence of instructions like: set aluin1 = r1

On Fri, Mar 25, 2016 at 01:23:03PM +0000, Renato Golin via llvm-dev wrote: > On 25 March 2016 at 04:11, Hal Finkel <hfinkel at anl.gov> wrote: > > As I understand it, the fundamental property being addresses here is: Are > > the semantics of scalar FP math the same as vector FP math? TTI seems like > > a good place to expose that information. If the semantics are indeed

From: Marcin Slusarz <marcin.slusarz at gmail.com> after this change nouveau passes all fill and blend tests of rendercheck (before: fill - 108/120, blend - 3323868/3569150) tested on NV34 Signed-off-by: Marcin Slusarz <marcin.slusarz at gmail.com> --- src/nv04_exa.c | 19 +++++++++---------- src/nv_accel_common.c | 5 ++++- 2 files changed, 13 insertions(+), 11

On Wed, Sep 20, 2017 at 12:20:40AM +0100, Jiong Wang via iovisor-dev wrote: > On 18/09/2017 22:29, Daniel Borkmann wrote: > > On 09/18/2017 10:47 PM, Jiong Wang wrote: > > > Hi, > > > > > >    Currently, LLVM eBPF backend always generate code in 64-bit mode, > > > this may > > > cause troubles when JITing to 32-bit targets. > > >

Dear group, Here is my data.frame : df <- structure(list(DESCRIPTION = c("PRM HGH GD ALU", "PRM HGH GD ALU", "PRIMARY NICKEL", "PRIMARY NICKEL", "PRIMARY NICKEL", "PRIMARY NICKEL", "STANDARD LEAD ", "STANDARD LEAD ", "STANDARD LEAD ", "STANDARD LEAD ", "STANDARD LEAD ",

On Sat, Sep 23, 2017 at 1:41 AM, Jakub Kicinski via iovisor-dev <iovisor-dev at lists.iovisor.org> wrote: > On Fri, 22 Sep 2017 22:03:47 -0700, Yonghong Song wrote: >> On 9/22/17 9:24 AM, Jakub Kicinski wrote: >> > On Thu, 21 Sep 2017 11:56:55 -0700, Alexei Starovoitov wrote: >> >> On Wed, Sep 20, 2017 at 12:20:40AM +0100, Jiong Wang via iovisor-dev wrote:

On Fri, Sep 20, 2013 at 3:30 AM, Liu Xin <navy.xliu at gmail.com> wrote: > Hi, Akira, > > I found you maintain mips MipsSchedule.td. does it correct? in > MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no > ByPass info out there. > are you sure this reflects the real R4xxx/R5xxx processors. > > why IILoad uses funcition unit ALU? >

From: alex at milivojevic.org > At various points in time Red Hat made some somewhat conflicting > decisions. The first was that Red Hat distributions must have NPTL. > For NPTL support, there are two components of system where it is > implemented, kernel and glibc. Back then glibc supported NPTL only > for i686. NPTL support was later backported to i586 and i486. Also remember

On 25 March 2016 at 04:11, Hal Finkel <hfinkel at anl.gov> wrote: > As I understand it, the fundamental property being addresses here is: Are the semantics of scalar FP math the same as vector FP math? TTI seems like a good place to expose that information. If the semantics are indeed different, then the vectorizer would require fast-math flags in order to vectorize FP operations

On 09/18/2017 10:47 PM, Jiong Wang wrote: > Hi, > > Currently, LLVM eBPF backend always generate code in 64-bit mode, this may > cause troubles when JITing to 32-bit targets. > > For example, it is quite common for XDP eBPF program to access some packet > fields through base + offset that the default eBPF will generate BPF_ALU64 for > the address formation, later when

Hi Jacob, As far as I know, an x86 'mov' instruction always uses an ALU resource. According to Agner Fog's documents (http://www.agner.org/optimize/), it can execute on port 0, 1 or 5 on recent architectures though. So it's not that likely to be resource limited. But it still occupies an instruction slot throughout the entire pipeline, costing power and potentially limiting other

Hi, I'm working on support for the latest generation of AMD GPUs (Southern Islands) in the R600 backend, and I need some advice on how to handle interactions between two different ALUs. The processors on Southern Islands GPUs are grouped into compute units, which contain 1 Scalar ALU (sALU) and 64 Vector ALUs (vALU). The sALU is mainly responsible for flow control (implemented using