Displaying 20 results from an estimated 400 matches similar to: "[LLVMdev] Simpler subreg ops in machine code IR"
2010 Jun 16
0
[LLVMdev] Simpler subreg ops in machine code IR
On Jun 15, 2010, at 2:48 PM, Jakob Stoklund Olesen wrote:
> I am considering adding a new target independent codegen-only COPY instruction to our MachineInstr representation. It would be used to replace INSERT_SUBREG, EXTRACT_SUBREG, and virtual register copies after instruction selection. Selection DAG still needs {INSERT,EXTRACT}_SUBREG, but they would not appear as MachineInstrs any longer.
2010 Jun 17
0
[LLVMdev] Loopinfo Analysis
Hi Hisham,
Most likely the basic blocks are the headers of two different loops. Try running viewCFG() on the function in question to see if this is the case.
Tom
----- Original Message -----
From: "Hisham Chowdhury" <hisham_chow at yahoo.com>
To: llvmdev at cs.uiuc.edu
Sent: Wednesday, June 16, 2010 7:22:00 PM GMT -05:00 US/Canada Eastern
Subject: [LLVMdev] Loopinfo Analysis
2010 Jun 16
2
[LLVMdev] Loopinfo Analysis
Hello,
I have a question regrading the analysis pass that generates loop info from an .ll code. My previous understanding was there will be just one loop header(in the loop info) for a particular loop. But, when i use isLoopHeader() member function from the loop info class I get 'true' return value for two different basic blocks. Note both basic blocks are loop conditional block(break
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
Hi all,
When compiling some programs using the Mips backend
i'm getting this assert message on lib/CodeGen/LiveInterval.cpp:227:
"Range is not entirely in interval!"
I don't know yet if it's something that is missing on the backend code or
why
the range to be removed it outside the interval, does anyone have any clue?
A more detailed output is attached.
The program i tried
2004 Jun 22
3
[LLVMdev] Linearscan allocator bug?
Folks,
I'm running into something which looks like a bug in linearscan allocator. Of
course I can't be 100% sure it's not some unobvious mistake on my part, so
I'd like to hear your opinion.
First, I attach two files -- LLVM asm and the asm for my target. The problem
with assembler is: on line 171 it uses register gr2, which is copied from gr6
above, on line 161. The only
2013 May 16
2
[LLVMdev] Combining physical registers
The function TII::canCombineSubRegIndices has been gone for a while now,
and I was wondering if there is a target-independent way of determining
if a certain set of physical registers "adds up" to a larger register.
For example, on X86, AL and AH together form AX. On Hexagon, R0 and R1
are D0.
The context here is an attempt to coalesce multiple loads/stores into
fewer loads/stores
2013 Oct 07
1
[LLVMdev] Subregister liveness tracking
I've been working on patches to improve subregister liveness tracking on
llvm and I wanted to inform the llvm community about the overal
design/motivation for them. I will send the patches to llvm-commits
later today.
Greetings
Matthias Braun
Subregisters in llvm
====================
Some targets can access registers in different ways resulting in wider or
narrower accesses. For
2013 Oct 08
2
[LLVMdev] Subregister liveness tracking
Currently it will always spill / restore the whole vreg but only
spilling the parts that are actually live would be a nice addition in
the future.
Looking at r192119': if "mtlo" writes to $LO and sets $HI to an
unpredictable value, then it should just have an additional (dead) def
operand for $hi, shouldn't it?
Greetings
Matthias
Am 10/8/13, 11:03 AM, schrieb Akira
2013 Oct 09
4
[LLVMdev] Subregister liveness tracking
On Oct 8, 2013, at 2:06 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> What I didn't mention in r192119 is that mthi/lo clobbers the other sub-register only if the contents of hi and lo are produced by mult or other arithmetic instructions (div, madd, etc.) It doesn't have this side-effect if it is produced by another mthi/lo. So I don't think making mthi/lo clobber the
2013 Oct 08
0
[LLVMdev] Subregister liveness tracking
What I didn't mention in r192119 is that mthi/lo clobbers the other
sub-register only if the contents of hi and lo are produced by mult or
other arithmetic instructions (div, madd, etc.) It doesn't have this
side-effect if it is produced by another mthi/lo. So I don't think making
mthi/lo clobber the other half would work.
For example, this is an illegal sequence of instructions,
2005 Sep 07
0
[LLVMdev] LiveIntervals, replace register with representative register?
On Wed, 2005-09-07 at 15:09 +0800, Tzu-Chien Chiu wrote:
> I don't understand the following code snippet in LiveIntervalAnalysis.cpp.
>
> Why changing the type of the opreand from a virtual register to a
> machine register? The register number (reg) is still a virtual
> register index (>1024).
>
>
> bool LiveIntervals::runOnMachineFunction(MachineFunction &fn)
2012 Mar 31
1
[LLVMdev] CompositeIndices
Does anyone know exactly what ComposerIndices in Target.td is all about?
I see just one place where it's used in X86 but it's not clear from the
comments in Target.td and it's one usage, exactly what this feature is
about.
Tia.
Reed
2005 Sep 07
4
[LLVMdev] LiveIntervals, replace register with representative register?
I don't understand the following code snippet in LiveIntervalAnalysis.cpp.
Why changing the type of the opreand from a virtual register to a
machine register? The register number (reg) is still a virtual
register index (>1024).
bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
// perform a final pass over the instructions and compute spill
// weights, coalesce
2008 Sep 16
1
[LLVMdev] PHI Elimination problem
Hi,
The PHI elimination pass calls the function copyRegToReg for copy
placement and then later tries to setkill to the temporary virtual
register used in copy placement. For this setkill action it looks only
in one instruction (last instruction for copyRegToReg) for virtual
register with no use.
My target has only one register and I can't do copyRegToReg in one
instruction only. So I
2007 Feb 22
2
[LLVMdev] Reference to recently created move
Hey, guys, I am creating some move instructions with
MRegisterInfo::copyRegToReg. How do I get a pointer to the instruction
that I just created? Is there a way to do something like:
// mbb is MachineBasicBlock, reg_info is MRegisterInfo
MachineBasicBlock::iterator iter = mbb.getFirstTerminator();
reg_info->copyRegToReg(mbb, iter, dst, src, rc);
iter--; (???)
MachineInstr *
2007 Jun 18
2
[LLVMdev] TargetRegisterClass for Physical Register
How do I get the TargetRegisterClass for a physical register?
SSARegMap::getRegClass only works for virtual registers.
-Dave
2007 Feb 22
0
[LLVMdev] Reference to recently created move
copyRegToReg() always insert the move instruction before "iter". Just
use prior(iter) after the insertion to reference the newly created
move instruction.
Evan
On Feb 21, 2007, at 11:17 PM, Fernando Magno Quintao Pereira wrote:
>
> Hey, guys, I am creating some move instructions with
> MRegisterInfo::copyRegToReg. How do I get a pointer to the instruction
> that I just
2007 Sep 05
1
[LLVMdev] Exception Problems
Hi Anton & Duncan,
When I try to compile on Darwin now, I get this:
$ /Volumes/Gir/devel/llvm/llvm-gcc-4.0.obj/gcc/xgcc <options> -o
eh_alloc.o
Assertion failed: (false && "Couldn't find the register class"),
function getPhysicalRegisterRegClass, file /Volumes/Gir/devel/llvm/
llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp, line 269.
2012 Jul 26
2
[LLVMdev] X86 sub_ss and sub_sd sub-register indexes
On Jul 26, 2012, at 10:28 AM, dag at cray.com wrote:
> Jakob Stoklund Olesen <jolesen at apple.com> writes:
>
>>> What happens if the result of the above pattern using COPY_TO_REGCLASS
>>> is spilled? Will we get a 64-bit store or a 128-bit store?
>>
>> This behavior isn't affected by the change. FR64 registers are spilled
>> with 64-bit
2010 Sep 01
1
[LLVMdev] equivalent IR, different asm
On Sep 1, 2010, at 11:14 AM, Dale Johannesen wrote:
>
> On Sep 1, 2010, at 6:25 AMPDT, Argyrios Kyrtzidis wrote:
>
>> The attached .ll files seem equivalent, but the resulting asm from
>> 'opt-fail.ll' causes a crash to webkit.
>> I suspect the usage of registers is wrong, can someone take a look ?
>
> Yes, the code here is wrong:
>
>> movl