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Displaying 20 results from an estimated 3000 matches similar to: "No subject"

2010 Mar 17
7
Asterisk DIES with no trace. PLEASE HELP!
Hello my friends We are having seriously problems with our asterisk server, our versions are as follows: WANPIPE Release: 3.4.7 Asterisk 1.4.21.2 Zaptel Version: 1.4.11 libpri version: 1.4.10.2 The symptoms are very weird, the CLI stop working suddenly, a core show channels shows MANY channels FREEZED, the incoming and outgoing calls stop working, the internal calls stop working, in resume we
2011 Mar 11
1
[Bug 704] Issue with "iptables -A OUTPUT -m string"
http://bugzilla.netfilter.org/show_bug.cgi?id=704 CZ <huangj at qualcomm.com> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|RESOLVED |REOPENED Resolution|FIXED | --- Comment #4 from CZ <huangj at qualcomm.com>
2005 Oct 23
6
configuring DNS
Hello I have DSL 2000 (2048 kbit/s download and 256 kbit/s upload) I have ping to fast sites very high: 64 bytes from w2.rc.vip.scd.yahoo.com (66.94.234.13): icmp_seq=3 ttl=50 time=2185 ms 64 bytes from w2.rc.vip.scd.yahoo.com (66.94.234.13): icmp_seq=4 ttl=50 time=1983 ms 64 bytes from w2.rc.vip.scd.yahoo.com (66.94.234.13): icmp_seq=5 ttl=50 time=1826 ms and I know why. I have 2 interfaces:
2007 Aug 13
2
Policy routing question
Hi, I have a testing multihome setup, with the default gateway being one of the links and using policy routing to honor requests for a specific link. Everything works as expected when I request a specific IP to bind to. But if I request a specific interface things fall apart in ways that I can not explain: default gw (WORKS) ---------- rabbit@Thesaurus:~$ ping -c 1 yahoo.com PING yahoo.com
2013 Oct 31
0
[LLVMdev] loop vectorizer
>> What needs to be done (on a high level) in order to have the auto vectorizer succeed on the test function as given erlier? > Maybe you could rewrite the loop in a way that will expose contiguous memory accesses. Is this something you could do ? > Hi Nadav, the only option I see is to unroll the loop by hand. Since the array access is consecutive over 4 loop iterations I gave it a
2013 Oct 31
2
[LLVMdev] loop vectorizer
On Oct 30, 2013, at 6:10 PM, Frank Winter <fwinter at jlab.org> wrote: > the only option I see is to unroll the loop by hand. Since the array access is consecutive over 4 loop iterations I gave it a try and unrolled the loop by a factor of 4. Which gives the following array accesses: > > loop iter 0: > index_0 = 0 index_1 = 4 > index_0 = 1 index_1 = 5 > index_0 = 2
2013 Oct 31
0
[LLVMdev] loop vectorizer
I tried the following on the hand-unrolled loop: const std::uint64_t ir0 = i*8+0; // working const std::uint64_t ir0 = i%4+0; // working const std::uint64_t ir0 = (i+0)%4; // not working '+0' means +1,+2,+3 in the unrolled iterations. 'Working' means the SLP vectorizer succeeded. Thus, when working 'towards' the correct index function, auto
2013 Oct 30
0
[LLVMdev] loop vectorizer
Well, they are not directly consecutive. They are consecutive with a constant offset or stride: ir1 = ir0 + 4 If I rewrite the function in this form void bar(std::uint64_t start, std::uint64_t end, float * __restrict__ c, float * __restrict__ a, float * __restrict__ b) { const std::uint64_t inner = 4; for (std::uint64_t i = start ; i < end ; ++i ) { const std::uint64_t ir0 = (
2009 Jan 08
1
Respuesta automática
 Xmas Gifts<br>  <br> My dear friends,Greetings from Doublewin-trade working team.<br>   <br>   I hope every thing is going on with you!Here,Thanks a lot for your support to us . We prepared some wonderful gifts for you!<br>   It seems that Christmas time is here once again, and it is time again to bring in the New Year. I wish you enjoy the Merry Christmas and your
2010 Sep 07
2
[LLVMdev] Complex regalloc contraints
Hi all, The machine I am targeting has some special requirements for some operations, say: ADD or1, ir1, r5 would add ir1 (input reg 1) and r5 and put the result in or1 (output reg 1). The point id that input and output regs have to go paired (this meaning an addition of ir1 with whatever always goes to or1, or an in general irX + whatever goes to orX). AFAIK, InstrInfo.td only allow
2013 Oct 30
0
[LLVMdev] loop vectorizer
Hi Frank, The access pattern to arrays a and b is non-linear. Unrolled loops are usually handled by the SLP-vectorizer. Are ir0 and ir1 consecutive for all values for i ? Thanks, Nadav On Oct 30, 2013, at 9:05 AM, Frank Winter <fwinter at jlab.org> wrote: > The loop vectorizer seems to be not able to vectorize the following code: > > void bar(std::uint64_t start,
2014 Mar 03
0
Re: 'virsh capabilities' on Debian Wheezy-amd64 reports different cpu to Wheezy-i386 (on same hardware)
On Mon, Mar 03, 2014 at 02:15:43PM +0000, Struan Bartlett wrote: > > > On 03/03/2014 13:42, Martin Kletzander wrote: > > On Mon, Mar 03, 2014 at 11:15:51AM +0000, Struan Bartlett wrote: > >> On 03/03/2014 10:55, Martin Kletzander wrote: > >>> On Mon, Mar 03, 2014 at 10:47:03AM +0000, Struan Bartlett wrote: > >>>> On 03/03/2014 10:44, Martin
2014 Mar 03
0
Re: 'virsh capabilities' on Debian Wheezy-amd64 reports different cpu to Wheezy-i386 (on same hardware)
On Mon, Mar 03, 2014 at 11:15:51AM +0000, Struan Bartlett wrote: > > On 03/03/2014 10:55, Martin Kletzander wrote: > > On Mon, Mar 03, 2014 at 10:47:03AM +0000, Struan Bartlett wrote: > >> On 03/03/2014 10:44, Martin Kletzander wrote: > >>> On Mon, Mar 03, 2014 at 10:30:11AM +0000, Struan Bartlett wrote: > >>>> Hi Martin > >>>> >
2015 Sep 29
3
Keepalived vrrp problem
Hey guys, I'm trying to install keepalived 1.2.19 on a centos 6.5 machine. I did an install from source. And when I start keepalived this is what I'm seeing in the logs. It's reporting that the VRRP_Instance(VI_1) Now in FAULT state. Here's more of that log entry: Sep 29 12:06:58 USECLSNDMNRDBA Keepalived_vrrp[44943]: VRRP Instance = VI_1 Sep 29 12:06:58 USECLSNDMNRDBA
2013 Oct 30
2
[LLVMdev] loop vectorizer
The loop vectorizer seems to be not able to vectorize the following code: void bar(std::uint64_t start, std::uint64_t end, float * __restrict__ c, float * __restrict__ a, float * __restrict__ b) { const std::uint64_t inner = 4; for (std::uint64_t i = start ; i < end ; ++i ) { const std::uint64_t ir0 = ( (i/inner) * 2 + 0 ) * inner + i%4; const std::uint64_t ir1 = ( (i/inner)
2010 Sep 07
0
[LLVMdev] Complex regalloc contraints
On Sep 7, 2010, at 3:01 AM, Carlos Sanchez de La Lama wrote: > The machine I am targeting has some special requirements for some > operations, say: > > ADD or1, ir1, r5 > > would add ir1 (input reg 1) and r5 and put the result in or1 (output reg > 1). The point id that input and output regs have to go paired (this > meaning an addition of ir1 with whatever always goes to
2013 Oct 30
2
[LLVMdev] loop vectorizer
The debug messages are misleading. They should read “trying to vectorize a list of …”; The problem is that the SCEV analysis is unable to detect that C[ir0] and C[ir1] are consecutive. Is this loop from an important benchmark ? Thanks, Nadav On Oct 30, 2013, at 11:13 AM, Frank Winter <fwinter at jlab.org> wrote: > The SLP vectorizer apparently did something in the prologue of the
2012 Aug 01
3
Neuralnet Error
I require some help in debugging this code  library(neuralnet) ir<-read.table(file="iris_data.txt",header=TRUE,row.names=NULL) ir1 <- data.frame(ir[1:100,2:6]) ir2 <- data.frame(ifelse(ir1$Species=="setosa",1,ifelse(ir1$Species=="versicolor",0,""))) colnames(ir2)<-("Output") ir3 <- data.frame(rbind(ir1[1:4],ir2))
2014 Mar 03
2
Re: 'virsh capabilities' on Debian Wheezy-amd64 reports different cpu to Wheezy-i386 (on same hardware)
On 03/03/2014 10:55, Martin Kletzander wrote: > On Mon, Mar 03, 2014 at 10:47:03AM +0000, Struan Bartlett wrote: >> On 03/03/2014 10:44, Martin Kletzander wrote: >>> On Mon, Mar 03, 2014 at 10:30:11AM +0000, Struan Bartlett wrote: >>>> Hi Martin >>>> >>>> Thanks for your response. Here's the output of that grep: >>>>
2013 Oct 30
0
[LLVMdev] loop vectorizer
The SLP vectorizer apparently did something in the prologue of the function (where storing of arguments on the stack happens) which then got eliminated later on (since I don't see any vector instructions in the final IR). Below the debug output of the SLP pass: Args: opt -O1 -vectorize-slp -debug loop.ll -S SLP: Analyzing blocks in _Z3barmmPfS_S_. SLP: Found 2 stores to vectorize. SLP: