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...; There doesn't seem to be a set of standard node types analogous to ADD / ADDC / ADDE for shift operations, which is really what I'm after here. >> >> I would very much appreciate any advice or insight you could provide on this matter. >> >> Thanks, >> ~Dave Waggoner / MathOnNapkins >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > > ______________________________________________...

...ter, though, is the MSP430, and it's still a bit experimental (though a very helpful example for me at times). Could I also ask whether you had to design your shift nodes with Glue or Chain operands? I haven't taken extra that step yet, but I imagine it will be necessary. Sincerely, ~Dave Waggoner / MathOnNapkins On Sun, Nov 10, 2013 at 1:35 PM, Steve Montgomery < stephen.montgomery3 at btinternet.com> wrote: > I forgot to mention that I used EXTRACT_ELEMENT in my backend to get the > high and low parts of an SDValue. > > On 10 Nov 2013, at 17:50, Steve Montgomery <...

...ntioned example: asl %b rol %c asl %b rol %c There doesn't seem to be a set of standard node types analogous to ADD / ADDC / ADDE for shift operations, which is really what I'm after here. I would very much appreciate any advice or insight you could provide on this matter. Thanks, ~Dave Waggoner / MathOnNapkins -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131109/c5b92890/attachment.html>

removeFromParent just unlinks it from the basic block and returns the removed instruction. It does not delete it. On Sun, Jan 20, 2013 at 9:54 PM, David Waggoner <mathonnapkins at gmail.com>wrote: > > Thanks for the suggestion, Duncan. > > I recently figured out that it had to do with how I was removing the > pseudo instruction in my overridden expandPostRAPseudo() implementation. > > // member function's signature > boo...

...gt; rol %c > > There doesn't seem to be a set of standard node types analogous to ADD / ADDC / ADDE for shift operations, which is really what I'm after here. > > I would very much appreciate any advice or insight you could provide on this matter. > > Thanks, > ~Dave Waggoner / MathOnNapkins > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

Thanks for the suggestion, Duncan. I recently figured out that it had to do with how I was removing the pseudo instruction in my overridden expandPostRAPseudo() implementation. // member function's signature bool TheInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator p_mi) // works bb.erase(p_mi); // produces the assertion / memory leak. p_mi->removeFromParent(); I should have

Hi all, We've just provisioned a new cluster of dovecot nodes running Centos and Dovecot 1.0.15 (we needed to match the original configuration, we're upgrading to 1.2 next week!). The nodes are currently equally allocated (50/50 split) to IMAP and POP3, with the intention to move them into a single cluster hosting both services in the next month. All the servers are of identical

...late fix this problem. Should I create a new pass to run after Post Regalloc to correct my Machine Functions? That seems like a last ditch effort at fixing the problem though, and I'd rather resolve it through some other means if possible. Any input would be much appreciated. Thank You, ~Dave Waggoner / MathOnNapkins -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131124/73bce9ed/attachment.html>

Dear All, I think I understand the motivation for these node types, but I'm not positive: " /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded /// integer shift operations, just like ADD/SUB_PARTS. The operation /// ordering is: /// [Lo,Hi] = op [LoLHS,HiLHS], Amt SHL_PARTS, SRA_PARTS, SRL_PARTS " Okay, for one thing, I can't

Hello, I've made some fair progress on a target for 6502 family CPUs recently, but I've run into an error I'm not sure how to address. I've ruminated over it for about a week now, trying various things and not having any success. It seems to scale with the number of routines in my .ll file, which I am trying to run through llc. I get the following stack dump from an assertion: