search for: vectorlength

...teoretical) coincide but low p-value indicate that i can reject hypotezis H0. For another side this p-value is most higer than p-value from second test (2.2e-16). Which result, test is most propertly? matr = rbind(c(1,2)) layout(matr) # length vectorSentence = 11999 vectorSentence <- c(....) vectorLength <- length(vectorSentence) # assume that we have a table(vectorSentence) # 1 2 3 4 5 6 7 8 9 # 512 1878 2400 2572 1875 1206 721 520 315 # Poisson parameter param <- fitdistr(vectorSentence, "poisson") # Expected density density.exp <- dpois(1:9, la...

...rovide an example? Also, what is the `tricky processing` you are referring to that the vectorizer should care about? For the case mentioned earlier: float MyAdd(float* a, int b) { return *a + b; } __declspec(vector_variant(implements(MyAdd(float *a, int b)), linear(a), vectorlength(8), nomask, processor(core_2nd_gen_avx))) __m256 __regcall MyAddVec(float* v_a, __m128i v_b1, __m128i v_b2) If FE emitted ;; Alwaysinline define <8 x float> @MyAddVec.abi_wrapper(float* %v_a, <8 x i32> %v_b) { ;; Not sure about the exact values in the mask...

...itions be stored? Using the example from https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-vector-variant: > > float MyAdd(float* a, int b) { return *a + b; } > __declspec(vector_variant(implements(MyAdd(float *a, int b)), > linear(a), vectorlength(8), > nomask, processor(core_2nd_gen_avx))) > __m256 __regcall MyAddVec(float* v_a, __m128i v_b1, __m128i v_b2) > > We need somehow communicate which lanes of widened "b" would map for the b1 parameter and which would go to the b2. If we only care abou...

...arameters positions be stored? Using the example from https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-vector-variant: float MyAdd(float* a, int b) { return *a + b; } __declspec(vector_variant(implements(MyAdd(float *a, int b)), linear(a), vectorlength(8), nomask, processor(core_2nd_gen_avx))) __m256 __regcall MyAddVec(float* v_a, __m128i v_b1, __m128i v_b2) We need somehow communicate which lanes of widened "b" would map for the b1 parameter and which would go to the b2. If we only care about single ABI (like...

On 03/02/2013 08:44 PM, Tobias Grosser wrote: > If the use of ivdep is correct, it seems necessary to _not_ annotate the loads > and stores from and to 't'. Only after 't' is moved into a register, the loop is > actually parallel on the IR level. I didn't realize this is a problem in general because in pocl we explicitly "privatize" the OpenCL C kernel

On 03/01/2013 10:05 PM, Redmond, Paul wrote: [...] > I have discovered that you can provide a custom inserter to IRBuilder (who knew!). This has basically solved all my problems and allowed me to generate the proper metadata with minimal changes to clang codegen. Currently it adds the metadata to all loads and stores but I don't think this is a problem and can be refined later if necessary.

...ld talk about unifying the two vector types. Alternatively, I believe > we could generalize the scalable vector type and my proposal, e.g., by > adding my proposed "vlentoken" to instructions on scalable vectors and > encode the "unknown, but fixed at program load time" vectorlength (i.e., > SVE) by using `token none` as vector length token. > > For the initial proposal, I did not want to impose either the loss in > optimization power or the additional complexity on scalable vectors, but if > you folks are fine with one of those options, I'd be very glad to...

...for SVE, we could talk about unifying the two vector types. Alternatively, I believe we could generalize the scalable vector type and my proposal, e.g., by adding my proposed "vlentoken" to instructions on scalable vectors and encode the "unknown, but fixed at program load time" vectorlength (i.e., SVE) by using `token none` as vector length token. I think your proposed function attribute 'inherits_vlen' would allow for outlining for SVE without causing problems, possibly using a TTI function to determine whether that was reasonable based on the backend. I don't think a...

RISC-V is an open and free instruction set architecture (ISA) used in numerous domains in industry and research. The vector extension (short: 'V') supplements the basic ISA with support for data parallel computations. This RFC sketches a strategy for targeting this instruction set extension in LLVM. Some but not all of what is proposed here has already been implemented out of tree. It is