Displaying 20 results from an estimated 61 matches for "trc".
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2008 Oct 13
2
[LLVMdev] INSERT_SUBREG node.
...FSR8RC, into a register type of FSR16RC.
when I use and INSERT_SUBREG with an SubIdx = 0, as you mentioned in
> v4= insert_subreg implicit_def, v1, 0
the following function returns an incorrect subregclass:
static const TargetRegisterClass*
getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx)
{
// Pick the register class of the subregister
TargetRegisterInfo::regclass_iterator I =
TRC->subregclasses_begin() + SubIdx-1;
assert(I < TRC->subregclasses_end() &&
"Invalid subregister index for register cl...
2008 Oct 14
0
[LLVMdev] INSERT_SUBREG node.
...C.
>
> when I use and INSERT_SUBREG with an SubIdx = 0, as you mentioned in
>
>> v4= insert_subreg implicit_def, v1, 0
>
> the following function returns an incorrect subregclass:
>
> static const TargetRegisterClass*
> getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned
> SubIdx)
> {
> // Pick the register class of the subregister
> TargetRegisterInfo::regclass_iterator I =
> TRC->subregclasses_begin() + SubIdx-1;
> assert(I < TRC->subregclasses_end() &&
> "Invalid subregister index for register...
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
...R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
class GR16_ ..... {
let SubRegClassList = [GR8];
}
Refer to below functions in ScheduleDAGEmit.cpp:
-----------------------------------------------
static const TargetRegisterClass*
getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned SubIdx)
{
// Pick the register class of the subregister
TargetRegisterInfo::regclass_iterator I =
TRC->subregclasses_begin() + SubIdx-1;
assert(I < TRC->subregclasses_end() &&
"Invalid subregister index for register class");
return *I;
}
/...
2005 Dec 13
3
[LLVMdev] The live interval of write-only registers
...live intervals should
not be joined with any other registers.
The only way I know to do this is defining several instruction
'templates' for an opcode (of course automatically generated by a
script) similar to the x86 code generator in LLVM:
InstrInfo.td:
// ORC: output register class
// TRC: temp register class
def ADDoaa : Inst<0x1234, (ops ORC:$dest, TRC:$src0, $TRC:src1), "add
$dest, $src0, $src1)
The letters (oaa) postfixed to the opcode (ADD) is the template. In
this way the output register won't be joined because they are of
different register classes.
However, th...
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
...= 0, as you mentioned in
>>>
>>>> v4= insert_subreg implicit_def, v1, 0
>>>
>>> the following function returns an incorrect subregclass:
>>>
>>> static const TargetRegisterClass*
>>> getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned
>>> SubIdx)
>>> {
>>> // Pick the register class of the subregister
>>> TargetRegisterInfo::regclass_iterator I =
>>> TRC->subregclasses_begin() + SubIdx-1;
>>> assert(I < TRC->subregclasses_end() &&
>>>...
2007 Sep 25
2
Constraining Predicted Values to be Greater Than 0
...ons.
There are some previous postings about constraining the coefficients, but this won't accomplish what I am trying to do. The coefficients can be negative, just as long as the predicted values are positive.
Thank you in advance for your time.
Westley A. Ritz
Analyst
215-641-2243
writz at trchome.com
TRC
www.trchome.com
2008 Oct 02
0
[LLVMdev] INSERT_SUBREG node.
On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote:
> What’s the value produced by an INSERT_SUBREG node? Is it a chain?
No, insert_subreg returns a value:
v1 = insert_subreg v2, v3, idx
v1 and v2 will have the same type, e.g. i16, and v3 must have a sub-
register type, e.g. i8.
> Can I use to set a superreg of i16 type with two i8 values, and use
> the supperreg as
2008 Oct 02
2
[LLVMdev] INSERT_SUBREG node.
What's the value produced by an INSERT_SUBREG node? Is it a chain?
Can I use to set a superreg of i16 type with two i8 values, and use the
supperreg as an operand somewhere else?
- Sanjiv
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2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
...>>
> >>>> v4= insert_subreg implicit_def, v1, 0
> >>>
> >>> the following function returns an incorrect subregclass:
> >>>
> >>> static const TargetRegisterClass*
> >>> getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned
> >>> SubIdx)
> >>> {
> >>> // Pick the register class of the subregister
> >>> TargetRegisterInfo::regclass_iterator I =
> >>> TRC->subregclasses_begin() + SubIdx-1;
> >>> assert(I < TRC->subregclasses_end...
2004 Jun 01
6
Permission Denied on ocfs directory
Skipped content of type multipart/alternative
2004 Jun 01
6
Permission Denied on ocfs directory
Skipped content of type multipart/alternative
2005 Dec 13
0
[LLVMdev] The live interval of write-only registers
..."register writes".
> The only way I know to do this is defining several instruction
> 'templates' for an opcode (of course automatically generated by a
> script) similar to the x86 code generator in LLVM:
>
> InstrInfo.td:
> // ORC: output register class
> // TRC: temp register class
>
> def ADDoaa : Inst<0x1234, (ops ORC:$dest, TRC:$src0, $TRC:src1), "add
> $dest, $src0, $src1)
>
> The letters (oaa) postfixed to the opcode (ADD) is the template. In
> this way the output register won't be joined because they are of
> differe...
2011 Jul 12
1
Can zpool permanent errors fixed by scrub?
.../perl/lib/5.8.3/sun4-solaris-thread-multi/auto/Socket/Socket.so
/zones/cctsprod/root/ccts/grid_agent/app/agent10g/lib32/libnmefsql.so
/zones/cctsprod/root/ccts/grid_agent/app/agent10g/network/log/sqlnet.log
/zones/cctsprod/root/ccts/grid_agent/app/agent10g/sysman/log/emagent.trc
/zones/cctsprod/root/ccts/grid_agent/app/agent10g/sysman/log/emdctl.trc
/zones/cctsprod/root/ccts/grid_agent/app/agent10g/sysman/log/emagent.nohup
/zones/cctsprod/root/ccts/oracle/app/product/10.2.0/lib/libons.so
/zones/cctsprod/root/ccts/oracle/app/product/10.2.0/li...
2008 Oct 16
0
[LLVMdev] INSERT_SUBREG node.
...gt;>>> v4= insert_subreg implicit_def, v1, 0
>>>>>
>>>>> the following function returns an incorrect subregclass:
>>>>>
>>>>> static const TargetRegisterClass*
>>>>> getSubRegisterRegClass(const TargetRegisterClass *TRC, unsigned
>>>>> SubIdx)
>>>>> {
>>>>> // Pick the register class of the subregister
>>>>> TargetRegisterInfo::regclass_iterator I =
>>>>> TRC->subregclasses_begin() + SubIdx-1;
>>>>> assert(I < TRC->...
2004 Nov 24
4
ORA-01207 after SAN maintenance
..., we got an ORA-01207, saying the control
file was older than the datafiles. Per Oracle support, we recreated the control file
and attempted to bring the db up with the new one. At this point we received the
following:
Errors in file /opt/oracle/product/9.2.0/admin/ENTPRD/udump/entprd2_ora_22596.trc:
ORA-00600: internal error code, arguments: [kcoapl_blkchk], [5], [393], [6101], [], [], [], []
There's a RAC bug entry for [kcoapl_blkchk], but it was for a 4-node RAC, ours is only
2 nodes, so Oracle internals support said they didn't think it applied to our case. We
ended up doing a po...
2010 May 27
1
[LLVMdev] Using LLVM to compile Objective-C on an Xbox 360
...lex Rosenberg wrote:
> PS3 is not "a Linux derivative." The compilers supplied by SCE for PS3
> game development are highly customized and support a customized ABI
> that will take some time to adjust LLVM and Clang to support.
>
> You'd likely also run afoul of a TRC or two, similar to the problems
> you'll face with Microsoft TCRs mentioned earlier.
>
> Alex
2007 Mar 04
1
[LLVMdev] infinite number of virtual registers - sorry, modified.
Hello.
I am making a backend for a virtual machine.
But it does assume infinite number of virtual registers unlike those of usual machines.
In this case, how can I implement this?
Would you mind telling me some tips?
Thank you so much.
Seung Jae Lee
2010 Dec 09
3
ZFS Prefetch Tuning
Hi All,
Is there a way to tune the zfs prefetch on a per pool basis? I have a
customer that is seeing slow performance on a pool the contains multiple
tablespaces from an Oracle database, looking at the LUNs associated to
that pool they are constantly at 80% - 100% busy. Looking at the output
from arcstat for the miss % on data, prefetch and metadata we are
getting around 5 - 10 % on data,
2007 Jun 08
0
OCFS error
...Current log# 3 seq# 30694 mem# 0: /u01/oradata/rgcsd/redo03a.log
Current log# 3 seq# 30694 mem# 1: /u01/oradata/rgcsd/redo03b.log
Fri Jun 8 01:10:49 2007
ARC0: Evaluating archive thread 2 sequence 30693
Fri Jun 8 01:10:50 2007
Errors in file /usr/app/oracle/admin/rgcsd/bdump/rgcsd2_arc0_2036.trc:
ORA-01264: Unable to create archived log file name
ORA-19800: Unable to initialize Oracle Managed Destination
Linux Error: 13: Permission denied
Fri Jun 8 01:10:50 2007
Errors in file /usr/app/oracle/admin/rgcsd/bdump/rgcsd2_arc0_2036.trc:
ORA-16032: parameter LOG_ARCHIVE_DEST_10 destination stri...
2012 Nov 15
1
[LLVMdev] problem trying to write an LLVM register-allocation pass
...about the code that gets a preg for a given vreg.
Previously,you gave me code that takes into account the "allocation
order" and the "reserved regs", including the following:
BitVector reservedRegs = TRI->getReservedRegs(Fn);
ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(Fn);
ArrayRef<uint16_t>::iterator rItr = rawOrder.begin();
while (rItr != rawOrder.end()) {
while (rItr != rawOrder.end() && reservedRegs.test(*rItr)) {
++rItr;
}
As I recall, this prevented some failed...