Displaying 11 results from an estimated 11 matches for "t1_w".
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
..., i32 2
call void @llvm.AMDGPU.store.output(float %23, i32 6)
%24 = extractelement <4 x float> %9, i32 3
call void @llvm.AMDGPU.store.output(float %24, i32 7)
ret void
}
# *** IR Dump Before Expand ISel Pseudo-instructions ***:
# Machine code for function main: SSA
Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3
Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
BB#0: derived from LLVM BB %0
Live Ins: %T1_W %T1_Z %T1_Y %T1_X
%vreg3<def> = COPY %T1_X; R600_TReg32:%vreg3
%vreg2<def> = COPY %T1_Y; R600_TReg32:%vreg2...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...32> %56, <1 x i32> %55, <1 x i32> <i32 1>
%58 = extractelement <1 x i32> %57, i32 0
br label %25
}
# *** IR Dump Before Expand ISel Pseudo-instructions ***:
# Machine code for function main: SSA
Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17
Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
BB#0: derived from LLVM BB %0
Live Ins: %T1_X %T1_Y %T1_Z %T1_W
%vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
%vreg15<def> = COPY %T1_Y; R600_TReg32:...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...<1 x i32> <i32 1>
> %58 = extractelement <1 x i32> %57, i32 0
> br label %25
> }
> # *** IR Dump Before Expand ISel Pseudo-instructions ***:
> # Machine code for function main: SSA
> Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17
> Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
>
> BB#0: derived from LLVM BB %0
> Live Ins: %T1_X %T1_Y %T1_Z %T1_W
> %vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
> %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
> %vreg15<...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...BB#3 apparently even if vreg32 lives in the 4 machine blocks
After joining, there are still vreg32 occurence in the machinefunction dump.
Before, the MF dump is :
_________________
# Machine code for function main: Post SSA
Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17
Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
BB#0: derived from LLVM BB %0
Live Ins: %T1_X %T1_Y %T1_Z %T1_W
%vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
%vreg15<def> = COPY %T1_Y; R600_TReg32:...
2012 Oct 25
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 25/10/2012 18:14, Vincent Lejeune wrote:
> When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg.
>
> If I look at the :
> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
>
> instructions ; it gets joined to :
> 928B%vreg34<def> = COPY %vreg48:sel_y;
>
> when vreg6 and
2012 Oct 26
1
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...32 lives in the 4 machine blocks
> After joining, there are still vreg32 occurence in the machinefunction dump.
>
> Before, the MF dump is :
> _________________
> # Machine code for function main: Post SSA
> Function Live Ins: %T1_X in %vreg14, %T1_Y in %vreg15, %T1_Z in %vreg16, %T1_W in %vreg17
> Function Live Outs: %T1_W %T1_Z %T1_Y %T1_X %T2_W %T2_Z %T2_Y %T2_X
>
> BB#0: derived from LLVM BB %0
> Live Ins: %T1_X %T1_Y %T1_Z %T1_W
> %vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
> %vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
> %vreg15<...
2012 Sep 27
1
[LLVMdev] Setting cl::opt<bool> EnablePhysicalJoin without a command line
...se live inst to represent OpenGL Input, which
are converted to vreg = COPY %PhysReg after instruction selection. For
instance, the following sample was generated when EnablePhysicalJoin is
true :
# Machine code for function main: Post SSA, not tracking liveness
Function Live Ins: %T2_X in %vreg0, %T1_W in %vreg1, %T1_Z in %vreg2, %
T1_Y in %vreg3, %T1_X in %vreg4
BB#0: derived from LLVM BB %main_body
Live Ins: %T2_X %T1_W %T1_Z %T1_Y %T1_X
%T1_X<def,undef> = KILL %T1_X<kill,undef>, %T1_XYZW<imp-def,undef>
R600_Export
%T1_XYZW<kill>, 0, 0, 0, 1, 2, 3
%T2_X&...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...re else.
>
It seems the PhiElim is working correctly, the output of --debug-only=regalloc shows that %vreg48 is a phi-join register, and intervals looks correct to me :
********** COMPUTING LIVE INTERVALS **********
********** Function: main
BB#0:# derived from
16B%vreg17<def> = COPY %T1_W<kill>; R600_TReg32:%vreg17
register: %vreg17 +[16r,352r:0)
32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16
register: %vreg16 +[32r,240r:0)
48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
register: %vreg15 +[48r,160r:0)
64B%vreg14<def> = COPY %T1_X...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...hiElim is working correctly, the output of --debug-only=regalloc
> shows that %vreg48 is a phi-join register, and intervals looks correct to me :
>
> ********** COMPUTING LIVE INTERVALS **********
> ********** Function: main
> BB#0:# derived from
> 16B%vreg17<def> = COPY %T1_W<kill>; R600_TReg32:%vreg17
> register: %vreg17 +[16r,352r:0)
> 32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16
> register: %vreg16 +[32r,240r:0)
> 48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
> register: %vreg15 +[48r,160r:0)
> 64B%...
2014 Feb 25
4
[LLVMdev] ScheduleDAGInstrs/R600 test potential issue with implicit defs
...h so that the
implicit-use is not ignored, there is a true dependency edge between
those two instructions, preventing bundling.
Removing only the implicit-defs alone has no effect in this example, as
then the implicit-use of T1_XYZW is then no longer removed and a true
dependency to the def of T1_W is added. Removing all implicit operands
however solves that (see attached patch/hack).
I would argue that the behaviour of ScheduleDAGInstrs::buildSchedGraph
for implicit operands is not correct, simply because changing the order
of the operands would already prevent the R600 packetizer from b...
2014 Feb 25
2
[LLVMdev] ScheduleDAGInstrs/R600 test potential issue with implicit defs
...3.4 and LLVM 3.4 with my patch applied right after the "Finalize machine instruction bundles" pass:
%T0_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T0_W<kill>, 0, 0, 0, -1, %ALU_LITERAL_X, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 3, 0
%T1_X<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %T1_W<kill>, 0, 0, 0, -1, %T0_W, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 0, 0, %T1_XYZW<imp-def>
%T1_W<def> = LSHL_eg 0, 0, 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, -1, %T0_W<kill>, 0, 0, 0, -1, 1, pred:%PRED_SEL_OFF, 255, 0, %T1_XYZW<imp-use,kill>, %T1_XYZW<imp-def>
Henc...